Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23738 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/Makefile b/lib/Target/PowerPC/Makefile
index 991626c449bdb5c59fa707cdbb6f55cc6ef72f71..3c864eb4cd6e5a7a7888b3cc3d17645b51a00257 100644 (file)
--- a/lib/Target/PowerPC/Makefile
+++ b/lib/Target/PowerPC/Makefile
@@ -8,12 +8,12 @@
 ##===----------------------------------------------------------------------===##
 LEVEL = ../../..
 LIBRARYNAME = LLVMPowerPC
-TARGET = PowerPC PPC32
+TARGET = PPC
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = PowerPCGenInstrNames.inc PowerPCGenRegisterNames.inc \
-                PowerPCGenAsmWriter.inc  PPC32GenCodeEmitter.inc \
-                PPC32GenRegisterInfo.h.inc PPC32GenRegisterInfo.inc \
-                PPC32GenInstrInfo.inc PPC32GenDAGISel.inc
+BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \
+                PPCGenAsmWriter.inc  PPCGenCodeEmitter.inc \
+                PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc \
+                PPCGenInstrInfo.inc PPCGenDAGISel.inc
 
 include $(LEVEL)/Makefile.common

diff --git a/lib/Target/PowerPC/PPC.h b/lib/Target/PowerPC/PPC.h
index b8adc2503891641226e59bd65498ebddd1b080d6..d58d2a6127a23059a8df1efafa3cd402820360b1 100644 (file)
--- a/lib/Target/PowerPC/PPC.h
+++ b/lib/Target/PowerPC/PPC.h
@@ -42,10 +42,10 @@ extern PPCTargetEnum PPCTarget;
 // Defines symbolic names for PowerPC registers.  This defines a mapping from
 // register name to register number.
 //
-#include "PowerPCGenRegisterNames.inc"
+#include "PPCGenRegisterNames.inc"
 
 // Defines symbolic names for the PowerPC instructions.
 //
-#include "PowerPCGenInstrNames.inc"
+#include "PPCGenInstrNames.inc"
 
 #endif

diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td
new file mode 100644 (file)
index 0000000..05f0d37
--- /dev/null
+++ b/lib/Target/PowerPC/PPC.td
@@ -0,0 +1,38 @@
+//===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+//
+// This is the top level entry point for the PowerPC target.
+//
+//===----------------------------------------------------------------------===//
+
+// Get the target-independent interfaces which we are implementing.
+//
+include "../Target.td"
+
+//===----------------------------------------------------------------------===//
+// Register File Description
+//===----------------------------------------------------------------------===//
+
+include "PowerPCRegisterInfo.td"
+include "PowerPCInstrInfo.td"
+
+def PPC : Target {
+  // Pointers on PPC are 32-bits in size.
+  let PointerType = i32;
+
+  // According to the Mach-O Runtime ABI, these regs are nonvolatile across
+  // calls
+  let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
+    R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
+    F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
+    F30, F31, CR2, CR3, CR4, LR];
+
+  // Pull in Instruction Info:
+  let InstructionSet = PowerPCInstrInfo;
+}

diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 539b821534d3e7b20ff035bd2b28a0e8622ea6fb..dab9b69d7f7e463a655b090d5356d373483cbbb0 100644 (file)
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -1,4 +1,4 @@
-//===-- PowerPCAsmPrinter.cpp - Print machine instrs to PowerPC assembly --===//
+//===-- PPCAsmPrinter.cpp - Print machine instrs to PowerPC assembly --===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -43,10 +43,10 @@ using namespace llvm;
 namespace {
   Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
 
-  struct PowerPCAsmPrinter : public AsmPrinter {
+  struct PPCAsmPrinter : public AsmPrinter {
     std::set<std::string> FnStubs, GVStubs, LinkOnceStubs;
 
-    PowerPCAsmPrinter(std::ostream &O, TargetMachine &TM)
+    PPCAsmPrinter(std::ostream &O, TargetMachine &TM)
       : AsmPrinter(O, TM), LabelNumber(0) {}
 
     /// Unique incrementer for label values for referencing Global values.
@@ -175,10 +175,10 @@ namespace {
   /// DarwinAsmPrinter - PowerPC assembly printer, customized for Darwin/Mac OS
   /// X
   ///
-  struct DarwinAsmPrinter : public PowerPCAsmPrinter {
+  struct DarwinAsmPrinter : public PPCAsmPrinter {
 
     DarwinAsmPrinter(std::ostream &O, TargetMachine &TM)
-      : PowerPCAsmPrinter(O, TM) {
+      : PPCAsmPrinter(O, TM) {
       CommentString = ";";
       GlobalPrefix = "_";
       ZeroDirective = "\t.space\t";  // ".space N" emits N zeros.
@@ -198,13 +198,13 @@ namespace {
 
   /// AIXAsmPrinter - PowerPC assembly printer, customized for AIX
   ///
-  struct AIXAsmPrinter : public PowerPCAsmPrinter {
+  struct AIXAsmPrinter : public PPCAsmPrinter {
     /// Map for labels corresponding to global variables
     ///
     std::map<const GlobalVariable*,std::string> GVToLabelMap;
 
     AIXAsmPrinter(std::ostream &O, TargetMachine &TM)
-      : PowerPCAsmPrinter(O, TM) {
+      : PPCAsmPrinter(O, TM) {
       CommentString = "#";
       GlobalPrefix = "_";
       ZeroDirective = "\t.space\t";  // ".space N" emits N zeros.
@@ -252,9 +252,9 @@ FunctionPass *llvm::createAIXAsmPrinter(std::ostream &o, TargetMachine &tm) {
 }
 
 // Include the auto-generated portion of the assembly writer
-#include "PowerPCGenAsmWriter.inc"
+#include "PPCGenAsmWriter.inc"
 
-void PowerPCAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
+void PPCAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
   const MRegisterInfo &RI = *TM.getRegisterInfo();
   int new_symbol;
 
@@ -340,7 +340,7 @@ void PowerPCAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
 /// printMachineInstruction -- Print out a single PowerPC MI in Darwin syntax to
 /// the current output stream.
 ///
-void PowerPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
+void PPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
   ++EmittedInsts;
 
   // Check for slwi/srwi mnemonics.

diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp
index af9c4cf43391c1a0d5f0b9b196a419bf0703dc5e..b64a6b8d0bc2e4d1a5e123531be386b3e8284620 100644 (file)
--- a/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -1,4 +1,4 @@
-//===-- PPC32CodeEmitter.cpp - JIT Code Emitter for PowerPC32 -----*- C++ -*-=//
+//===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC32 -----*- C++ -*-=//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -24,7 +24,7 @@
 using namespace llvm;
 
 namespace {
-  class PPC32CodeEmitter : public MachineFunctionPass {
+  class PPCCodeEmitter : public MachineFunctionPass {
     TargetMachine &TM;
     MachineCodeEmitter &MCE;
 
@@ -38,7 +38,7 @@ namespace {
     int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
 
   public:
-    PPC32CodeEmitter(TargetMachine &T, MachineCodeEmitter &M)
+    PPCCodeEmitter(TargetMachine &T, MachineCodeEmitter &M)
       : TM(T), MCE(M) {}
 
     const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
@@ -76,13 +76,13 @@ namespace {
 bool PPC32TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
                                                     MachineCodeEmitter &MCE) {
   // Machine code emitter pass for PowerPC
-  PM.add(new PPC32CodeEmitter(*this, MCE));
+  PM.add(new PPCCodeEmitter(*this, MCE));
   // Delete machine code for this function after emitting it
   PM.add(createMachineCodeDeleter());
   return false;
 }
 
-bool PPC32CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
+bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
   MCE.startFunction(MF);
   MCE.emitConstantPool(MF.getConstantPool());
   for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
@@ -114,7 +114,7 @@ bool PPC32CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
   return false;
 }
 
-void PPC32CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
+void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
   assert(!PICEnabled && "CodeEmitter does not support PIC!");
   BBLocations[&MBB] = MCE.getCurrentPCValue();
   for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
@@ -175,7 +175,7 @@ static unsigned enumRegToMachineReg(unsigned enumReg) {
   }
 }
 
-int PPC32CodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
+int PPCCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
 
   int rv = 0; // Return value; defaults to 0 for unhandled cases
                   // or things that get fixed up later by the JIT.
@@ -260,5 +260,5 @@ int PPC32CodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
   return rv;
 }
 
-#include "PPC32GenCodeEmitter.inc"
+#include "PPCGenCodeEmitter.inc"
 

diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index eb6a5d7b2068bce80cb86e53c62c5c0ca34abbbf..35087a5741ec79f82a86f53bd418f6f4c2a9a406 100644 (file)
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -90,7 +90,7 @@ namespace {
     } 
 
 // Include the pieces autogenerated from the target description.
-#include "PPC32GenDAGISel.inc"
+#include "PPCGenDAGISel.inc"
     
 private:
     SDOperand SelectDYNAMIC_STACKALLOC(SDOperand Op);

diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 2af109935549159a5fbecc1ea2609b7f8bef058d..d4910dc377d47bedb2cd6fa0dd2ecb350a4e1c83 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -12,14 +12,14 @@
 //===----------------------------------------------------------------------===//
 
 #include "PPC32InstrInfo.h"
-#include "PPC32GenInstrInfo.inc"
+#include "PPCGenInstrInfo.inc"
 #include "PowerPC.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include <iostream>
 using namespace llvm;
 
 PPC32InstrInfo::PPC32InstrInfo()
-  : TargetInstrInfo(PPC32Insts, sizeof(PPC32Insts)/sizeof(PPC32Insts[0])) {}
+  : TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])) {}
 
 bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI,
                                  unsigned& sourceReg,

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 445c324903eb0189e5f4affa91ff8b1f27397b85..4b2e5ac02c9589a5b73e649799a2d3a281425185 100644 (file)
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -32,7 +32,7 @@
 using namespace llvm;
 
 PPC32RegisterInfo::PPC32RegisterInfo()
-  : PPC32GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
+  : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
   ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;
   ImmToIdxMap[PPC::LBZ]  = PPC::LBZX;   ImmToIdxMap[PPC::STB]  = PPC::STBX;
   ImmToIdxMap[PPC::LHZ]  = PPC::LHZX;   ImmToIdxMap[PPC::LHA]  = PPC::LHAX;
@@ -342,5 +342,5 @@ void PPC32RegisterInfo::emitEpilogue(MachineFunction &MF,
   }
 }
 
-#include "PPC32GenRegisterInfo.inc"
+#include "PPCGenRegisterInfo.inc"
 

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h
index 3311263dc0c2b24eab9395068e0fabf2c9f8fe98..ed361578e5c76ea76f295bea633fa6ac451697ff 100644 (file)
--- a/lib/Target/PowerPC/PPCRegisterInfo.h
+++ b/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -15,14 +15,14 @@
 #define POWERPC32_REGISTERINFO_H
 
 #include "PowerPC.h"
-#include "PPC32GenRegisterInfo.h.inc"
+#include "PPCGenRegisterInfo.h.inc"
 #include <map>
 
 namespace llvm {
 
 class Type;
 
-class PPC32RegisterInfo : public PPC32GenRegisterInfo {
+class PPC32RegisterInfo : public PPCGenRegisterInfo {
   std::map<unsigned, unsigned> ImmToIdxMap;
 public:
   PPC32RegisterInfo();