include "../Target.td"
//===----------------------------------------------------------------------===//
-// PowerPC Subtarget features.
+// SPARC Subtarget features.
//
-def Feature64Bit : SubtargetFeature<"64bit", "bool", "Is64Bit",
- "Enable 64-bit instructions">;
-
+def FeatureV9
+ : SubtargetFeature<"v9", "bool", "IsV9",
+ "Enable SPARC-V9 instructions">;
+def FeatureV8Deprecated
+ : SubtargetFeature<"deprecated-v8", "bool", "V8DeprecatedInsts",
+ "Enable deprecated V8 instructions in V9 mode">;
+def FeatureVIS
+ : SubtargetFeature<"vis", "bool", "IsVIS",
+ "Enable UltraSPARC Visual Instruction Set extensions">;
//===----------------------------------------------------------------------===//
// Register File Description
// SPARC processors supported.
//===----------------------------------------------------------------------===//
-def : Processor<"generic", NoItineraries, []>;
-def : Processor<"v8", NoItineraries, []>;
-def : Processor<"v9", NoItineraries, [Feature64Bit]>;
+class Proc<string Name, list<SubtargetFeature> Features>
+ : Processor<Name, NoItineraries, Features>;
+
+def : Proc<"generic", []>;
+def : Proc<"v8", []>;
+def : Proc<"supersparc", []>;
+def : Proc<"sparclite", []>;
+def : Proc<"f934", []>;
+def : Proc<"hypersparc", []>;
+def : Proc<"sparclite86x", []>;
+def : Proc<"sparclet", []>;
+def : Proc<"tsc701", []>;
+def : Proc<"v9", [FeatureV9]>;
+def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated]>;
+def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated]>;
+def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
+
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//
//===--------------------------------------------------------------------===//
-/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
+/// SparcV8DAGToDAGISel - SPARC specific code to select Sparc V8 machine
/// instructions for SelectionDAG operations.
///
namespace {
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
virtual const char *getPassName() const {
- return "PowerPC DAG->DAG Pattern Instruction Selection";
+ return "SparcV8 DAG->DAG Pattern Instruction Selection";
}
// Include the pieces autogenerated from the target description.
}
-/// createPPCISelDag - This pass converts a legalized DAG into a
-/// PowerPC-specific DAG, ready for instruction scheduling.
+/// createSparcV8ISelDag - This pass converts a legalized DAG into a
+/// SPARC-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
return new SparcV8DAGToDAGISel(TM);
// Parse features string.
ParseSubtargetFeatures(FS, CPU);
-};
\ No newline at end of file
+};
class Module;
class SparcV8Subtarget : public TargetSubtarget {
- bool Is64Bit;
+ bool IsV9;
+ bool V8DeprecatedInsts;
+ bool IsVIS;
public:
SparcV8Subtarget(const Module &M, const std::string &FS);
- bool is64Bit() const { return Is64Bit; }
+ bool isV9() const { return IsV9; }
+ bool isVIS() const { return IsVIS; }
+ bool useDeprecatedV8Instructions() const { return V8DeprecatedInsts; }
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
include "../Target.td"
//===----------------------------------------------------------------------===//
-// PowerPC Subtarget features.
+// SPARC Subtarget features.
//
-def Feature64Bit : SubtargetFeature<"64bit", "bool", "Is64Bit",
- "Enable 64-bit instructions">;
-
+def FeatureV9
+ : SubtargetFeature<"v9", "bool", "IsV9",
+ "Enable SPARC-V9 instructions">;
+def FeatureV8Deprecated
+ : SubtargetFeature<"deprecated-v8", "bool", "V8DeprecatedInsts",
+ "Enable deprecated V8 instructions in V9 mode">;
+def FeatureVIS
+ : SubtargetFeature<"vis", "bool", "IsVIS",
+ "Enable UltraSPARC Visual Instruction Set extensions">;
//===----------------------------------------------------------------------===//
// Register File Description
// SPARC processors supported.
//===----------------------------------------------------------------------===//
-def : Processor<"generic", NoItineraries, []>;
-def : Processor<"v8", NoItineraries, []>;
-def : Processor<"v9", NoItineraries, [Feature64Bit]>;
+class Proc<string Name, list<SubtargetFeature> Features>
+ : Processor<Name, NoItineraries, Features>;
+
+def : Proc<"generic", []>;
+def : Proc<"v8", []>;
+def : Proc<"supersparc", []>;
+def : Proc<"sparclite", []>;
+def : Proc<"f934", []>;
+def : Proc<"hypersparc", []>;
+def : Proc<"sparclite86x", []>;
+def : Proc<"sparclet", []>;
+def : Proc<"tsc701", []>;
+def : Proc<"v9", [FeatureV9]>;
+def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated]>;
+def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated]>;
+def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
+
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//
//===--------------------------------------------------------------------===//
-/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
+/// SparcV8DAGToDAGISel - SPARC specific code to select Sparc V8 machine
/// instructions for SelectionDAG operations.
///
namespace {
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
virtual const char *getPassName() const {
- return "PowerPC DAG->DAG Pattern Instruction Selection";
+ return "SparcV8 DAG->DAG Pattern Instruction Selection";
}
// Include the pieces autogenerated from the target description.
}
-/// createPPCISelDag - This pass converts a legalized DAG into a
-/// PowerPC-specific DAG, ready for instruction scheduling.
+/// createSparcV8ISelDag - This pass converts a legalized DAG into a
+/// SPARC-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
return new SparcV8DAGToDAGISel(TM);
// Parse features string.
ParseSubtargetFeatures(FS, CPU);
-};
\ No newline at end of file
+};
class Module;
class SparcV8Subtarget : public TargetSubtarget {
- bool Is64Bit;
+ bool IsV9;
+ bool V8DeprecatedInsts;
+ bool IsVIS;
public:
SparcV8Subtarget(const Module &M, const std::string &FS);
- bool is64Bit() const { return Is64Bit; }
+ bool isV9() const { return IsV9; }
+ bool isVIS() const { return IsVIS; }
+ bool useDeprecatedV8Instructions() const { return V8DeprecatedInsts; }
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.