if (opSize > destSize ||
(val->getType()->isSigned()
- && destSize < target.getTargetData().getIntegerRegize()))
+ && destSize < target.getTargetData().getIntegerRegSize()))
{ // operand is larger than dest,
// OR both are equal but smaller than the full register size
// AND operand is signed, so it may have extra sign bits:
Value* shiftDest = destVal;
unsigned opSize = target.getTargetData().getTypeSize(argVal1->getType());
if ((shiftOpCode == SLL || shiftOpCode == SLLX)
- && opSize < target.getTargetData().getIntegerRegize())
+ && opSize < target.getTargetData().getIntegerRegSize())
{ // put SLL result into a temporary
shiftDest = new TmpInstruction(argVal1, optArgVal2, "sllTmp");
mcfi.addTemp(shiftDest);
.addReg(dest, MOTy::Def);
mvec.push_back(M);
}
- else if (destSize < target.getTargetData().getIntegerRegize())
+ else if (destSize < target.getTargetData().getIntegerRegSize())
assert(0 && "Unsupported type size: 32 < size < 64 bits");
}
}