#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
+ <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
<&cru PLL_CPLL>, <&cru PLL_GPLL>,
<&cru PLL_NPLL>, <&cru PLL_MPLL>,
<&cru PLL_WPLL>, <&cru PLL_BPLL>,
<&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
<&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>;
assigned-clock-rates =
+ <0>, <0>,
<750000000>, <576000000>,
<594000000>, <594000000>,
<960000000>, <520000000>,
<375000000>, <288000000>,
<100000000>, <100000000>;
+ assigned-clock-parents =
+ <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>;
};
grf: syscon@ff770000 {