// FIXME: the register order should be defined in terms of the preferred
// allocation order...
//
-def IntRegs : RegisterClass<i32, 8, [G1, G2, G3, G4, G5, G6, G7,
- O0, O1, O2, O3, O4, O5, O7,
- L0, L1, L2, L3, L4, L5, L6, L7,
+def IntRegs : RegisterClass<i32, 8, [L0, L1, L2, L3, L4, L5, L6, L7,
I0, I1, I2, I3, I4, I5,
+ G1, G2, G3, G4, G5, G6, G7,
+ O0, O1, O2, O3, O4, O5, O7,
// Non-allocatable regs
O6, I6, I7, G0]> {
let Methods = [{
// FIXME: the register order should be defined in terms of the preferred
// allocation order...
//
-def IntRegs : RegisterClass<i32, 8, [G1, G2, G3, G4, G5, G6, G7,
- O0, O1, O2, O3, O4, O5, O7,
- L0, L1, L2, L3, L4, L5, L6, L7,
+def IntRegs : RegisterClass<i32, 8, [L0, L1, L2, L3, L4, L5, L6, L7,
I0, I1, I2, I3, I4, I5,
+ G1, G2, G3, G4, G5, G6, G7,
+ O0, O1, O2, O3, O4, O5, O7,
// Non-allocatable regs
O6, I6, I7, G0]> {
let Methods = [{