[ARM] tegra: iomap: Add missing devices, fix use of SZ_8

Adds gart, hdmi, and pwm controllers to mach/iomap.h
SZ_* stops at SZ_16; just use a constant value of 8 for the timer
aperture sizes.

Change-Id: I4bbf1ca37b65698f707a277575054610ee6ca445
Signed-off-by: Gary King <gking@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>

diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index 325eca37348fab1ef76a8adb8453a10b1c7de42a..b35d3e3910b56b7c1f546a78425bfbd3e53f3494 100644 (file)
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -41,6 +41,12 @@
 #define TEGRA_DISPLAY2_BASE            0x54240000
 #define TEGRA_DISPLAY2_SIZE            SZ_256K
 
+#define TEGRA_HDMI_BASE                        0x54280000
+#define TEGRA_HDMI_SIZE                        SZ_256K
+
+#define TEGRA_GART_BASE                        0x58000000
+#define TEGRA_GART_SIZE                        SZ_32M
+
 #define TEGRA_PRIMARY_ICTLR_BASE       0x60004000
 #define TEGRA_PRIMARY_ICTLR_SIZE       SZ_64
 
@@ -54,19 +60,19 @@
 #define TEGRA_QUATERNARY_ICTLR_SIZE    SZ_64
 
 #define TEGRA_TMR1_BASE                        0x60005000
-#define TEGRA_TMR1_SIZE                        SZ_8
+#define TEGRA_TMR1_SIZE                        8
 
 #define TEGRA_TMR2_BASE                        0x60005008
-#define TEGRA_TMR2_SIZE                        SZ_8
+#define TEGRA_TMR2_SIZE                        8
 
 #define TEGRA_TMRUS_BASE               0x60005010
 #define TEGRA_TMRUS_SIZE               SZ_64
 
 #define TEGRA_TMR3_BASE                        0x60005050
-#define TEGRA_TMR3_SIZE                        SZ_8
+#define TEGRA_TMR3_SIZE                        8
 
 #define TEGRA_TMR4_BASE                        0x60005058
-#define TEGRA_TMR4_SIZE                        SZ_8
+#define TEGRA_TMR4_SIZE                        8
 
 #define TEGRA_CLK_RESET_BASE           0x60006000
 #define TEGRA_CLK_RESET_SIZE           SZ_4K
@@ -140,6 +146,18 @@
 #define TEGRA_PWFM_BASE                        0x7000A000
 #define TEGRA_PWFM_SIZE                        SZ_256
 
+#define TEGRA_PWFM0_BASE               0x7000A000
+#define TEGRA_PWFM0_SIZE               4
+
+#define TEGRA_PWFM1_BASE               0x7000A010
+#define TEGRA_PWFM1_SIZE               4
+
+#define TEGRA_PWFM2_BASE               0x7000A020
+#define TEGRA_PWFM2_SIZE               4
+
+#define TEGRA_PWFM3_BASE               0x7000A030
+#define TEGRA_PWFM3_SIZE               4
+
 #define TEGRA_MIPI_BASE                        0x7000B000
 #define TEGRA_MIPI_SIZE                        SZ_256