ARM assembly parsing and encoding for SWP[B] instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136098 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index 322f700b366a0f764d3fbe1883d54b581a69be4b..3c1ff6c7d0cefa4db3d2adbd8fb3e5332af996c3 100644 (file)
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -442,14 +442,14 @@ class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
   let Inst{3-0}   = Rt;
 }
 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
-  : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> {
+  : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
   bits<4> Rt;
   bits<4> Rt2;
-  bits<4> Rn;
+  bits<4> addr;
   let Inst{27-23} = 0b00010;
   let Inst{22} = b;
   let Inst{21-20} = 0b00;
-  let Inst{19-16} = Rn;
+  let Inst{19-16} = addr;
   let Inst{15-12} = Rt;
   let Inst{11-4} = 0b00001001;
   let Inst{3-0} = Rt2;

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index c3b11442d30d425b87de1ad57f82c7d216519a33..c5860ab280de36687ba5d58da5cf26e551d82eb0 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -3659,10 +3659,10 @@ def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
   let Inst{31-0} = 0b11110101011111111111000000011111;
 }
 
-// SWP/SWPB are deprecated in V6/V7 and for disassembly only.
+// SWP/SWPB are deprecated in V6/V7.
 let mayLoad = 1, mayStore = 1 in {
-def SWP  : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp", []>;
-def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb", []>;
+def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addrmode7:$addr), "swp", []>;
+def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addrmode7:$addr), "swpb", []>;
 }
 
 //===----------------------------------------------------------------------===//

diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s
index 13afd8b583ea1a82dcad43ad78ed001ad1a68866..adbdf9e5966ae1a24f79354ea4071d4c04eebd37 100644 (file)
--- a/test/MC/ARM/basic-arm-instructions.s
+++ b/test/MC/ARM/basic-arm-instructions.s
@@ -1763,3 +1763,15 @@ _func:
 @ CHECK: svc   #16                     @ encoding: [0x10,0x00,0x00,0xef]
 @ CHECK: svc   #0                      @ encoding: [0x00,0x00,0x00,0xef]
 @ CHECK: svc   #16777215               @ encoding: [0xff,0xff,0xff,0xef]
+
+
+@------------------------------------------------------------------------------
+@ SWP/SWPB
+@------------------------------------------------------------------------------
+        swp r1, r2, [r3]
+        swp r4, r4, [r6]
+        swpb r5, r1, [r9]
+
+@ CHECK: swp   r1, r2, [r3]            @ encoding: [0x92,0x10,0x03,0xe1]
+@ CHECK: swp   r4, r4, [r6]            @ encoding: [0x94,0x40,0x06,0xe1]
+@ CHECK: swpb  r5, r1, [r9]            @ encoding: [0x91,0x50,0x49,0xe1]