clk: rockchip: add clock ids for vip of RK3368 SoCs

Change-Id: I73ac0fd0010d0dc95c6da0770f85d7b35a11a628
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index e4682106a9e8d22aae77fdb92cc27fa40d029ccd..899a736a5f38efd65fbde7cf9f1340a119631cc9 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -445,10 +445,10 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
        GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
                        RK3368_CLKGATE_CON(4), 12, GFLAGS),
 
-       COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
+       COMPOSITE_NODIV(SCLK_VIP_SRC, "vip_src", mux_pll_src_cpll_gpll_p, 0,
                        RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,
                        RK3368_CLKGATE_CON(4), 5, GFLAGS),
-       COMPOSITE_NOGATE(0, "sclk_vip_out", mux_vip_out_p, 0,
+       COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
                        RK3368_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS),
 
        COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,

diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
index d929b6c53d2875e70ed91725366081eff69f26e7..08a36db4ebf40b237bcf24998ccdc0a21825051b 100644 (file)
--- a/include/dt-bindings/clock/rk3368-cru.h
+++ b/include/dt-bindings/clock/rk3368-cru.h
@@ -84,6 +84,8 @@
 #define SCLK_MACREF_OUT                128
 #define SCLK_MIPIDSI_24M       129
 #define SCLK_CRYPTO            130
+#define SCLK_VIP_SRC           131
+#define SCLK_VIP_OUT           132
 
 #define DCLK_VOP               190
 #define MCLK_CRYPTO            191