* Added undef patterns.

* Some reorg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25163 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 22c7f7cf83c5d71c1707a62f1b4caf6883b2406d..723cb4dd350021007061592de0a030ed29837228 100644 (file)
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -550,15 +550,6 @@ SDOperand X86DAGToDAGISel::Select(SDOperand N) {
         return CodeGenMap[N] = CurDAG->getTargetNode(Opc, VT, Result);
       break;
     }
-
-    case ISD::UNDEF: {
-      Opc = (NVT == MVT::f64) ? (X86Vector >= SSE2 ? X86::FLD0SD : X86::FpLD0)
-                              : X86::IMPLICIT_DEF;
-      if (N.Val->hasOneUse())
-        return CurDAG->SelectNodeTo(N.Val, Opc, NVT);
-      else
-        return CodeGenMap[N] = CurDAG->getTargetNode(Opc, NVT);
-    }
   }
 
   return SelectCode(N);

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 23bee2e972d4c43cbdeefa48423d9e80450c3d6c..833f1eaf4c33093082b66d912b5c7f9035c91c34 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -368,6 +368,16 @@ def ADJCALLSTACKUP   : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2),
                          [(X86callseq_end imm:$amt1, imm:$amt2)]>;
 def IMPLICIT_USE     : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>;
 def IMPLICIT_DEF     : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>;
+def IMPLICIT_DEF_R8  : I<0, Pseudo, (ops R8:$dst),
+                         "#IMPLICIT_DEF $dst",
+                         [(set R8:$dst, (undef))]>;
+def IMPLICIT_DEF_R16  : I<0, Pseudo, (ops R16:$dst),
+                         "#IMPLICIT_DEF $dst",
+                         [(set R16:$dst, (undef))]>;
+def IMPLICIT_DEF_R32  : I<0, Pseudo, (ops R32:$dst),
+                         "#IMPLICIT_DEF $dst",
+                         [(set R32:$dst, (undef))]>;
+
 let isTerminator = 1 in
   let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
     def FP_REG_KILL  : I<0, Pseudo, (ops), "#FP_REG_KILL", []>;
@@ -438,11 +448,6 @@ let isCall = 1, noResults = 1 in
                       [(X86call (loadi32 addr:$dst))]>;
   }
 
-def : Pat<(X86call tglobaladdr:$dst),
-          (CALLpcrel32 tglobaladdr:$dst)>;
-def : Pat<(X86call externalsym:$dst),
-          (CALLpcrel32 externalsym:$dst)>;
-
 // Tail call stuff.
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
   def TAILJMPd : IBr<0xE9, (ops calltarget:$dst), "jmp $dst  # TAIL CALL", []>;
@@ -1890,25 +1895,6 @@ def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
 
 } // end Two Address instructions
 
-// X86 specific add which produces a flag.
-def : Pat<(X86addflag R32:$src1, R32:$src2),
-          (ADD32rr R32:$src1, R32:$src2)>;
-def : Pat<(X86addflag R32:$src1, (load addr:$src2)),
-          (ADD32rm R32:$src1, addr:$src2)>;
-def : Pat<(X86addflag R32:$src1, imm:$src2),
-          (ADD32ri R32:$src1, imm:$src2)>;
-def : Pat<(X86addflag R32:$src1, i32immSExt8:$src2),
-          (ADD32ri8 R32:$src1, i32immSExt8:$src2)>;
-
-def : Pat<(X86subflag R32:$src1, R32:$src2),
-          (SUB32rr R32:$src1, R32:$src2)>;
-def : Pat<(X86subflag R32:$src1, (load addr:$src2)),
-          (SUB32rm R32:$src1, addr:$src2)>;
-def : Pat<(X86subflag R32:$src1, imm:$src2),
-          (SUB32ri R32:$src1, imm:$src2)>;
-def : Pat<(X86subflag R32:$src1, i32immSExt8:$src2),
-          (SUB32ri8 R32:$src1, i32immSExt8:$src2)>;
-
 // Suprisingly enough, these are not two address instructions!
 def IMUL16rri  : Ii16<0x69, MRMSrcReg,                      // R16 = R16*I16
                       (ops R16:$dst, R16:$src1, i16imm:$src2),
@@ -2284,20 +2270,6 @@ def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src),
                    "movz{wl|x} {$src, $dst|$dst, $src}",
                    [(set R32:$dst, (zextloadi32i16 addr:$src))]>, TB;
 
-// Handling 1 bit zextload and sextload
-def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8  addr:$src)>;
-def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8  addr:$src)>;
-def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8  addr:$src)>;
-def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8  addr:$src)>;
-
-// Handling 1 bit extload
-def : Pat<(extloadi8i1 addr:$src), (MOV8rm  addr:$src)>;
-
-// Modeling anyext as zext
-def : Pat<(i16 (anyext R8 :$src)), (MOVZX16rr8  R8 :$src)>;
-def : Pat<(i32 (anyext R8 :$src)), (MOVZX32rr8  R8 :$src)>;
-def : Pat<(i32 (anyext R16:$src)), (MOVZX32rr16 R16:$src)>;
-
 //===----------------------------------------------------------------------===//
 // XMM Floating point support (requires SSE / SSE2)
 //===----------------------------------------------------------------------===//
@@ -2555,25 +2527,25 @@ def CMPSDrm : I<0xC2, MRMSrcMem,
 // FPI - Floating Point Instruction template.
 class FPI<bits<8> o, Format F, dag ops, string asm> : I<o, F, ops, asm, []> {}
 
-// FpI - Floating Point Psuedo Instruction template.
-class FpI<dag ops, FPFormat fp, list<dag> pattern>
-  : X86Inst<0, Pseudo, NoImm, ops, "">, Requires<[FPStack]> {
+// FpI_ - Floating Point Psuedo Instruction template. Not Predicated.
+class FpI_<dag ops, FPFormat fp, list<dag> pattern>
+  : X86Inst<0, Pseudo, NoImm, ops, ""> {
   let FPForm = fp; let FPFormBits = FPForm.Value;
   let Pattern = pattern;
 }
 
 // Random Pseudo Instructions.
-def FpGETRESULT : FpI<(ops RFP:$dst), SpecialFP, []>;   // FPR = ST(0)
-
-// Do not inline into instruction def. since it isn't predicated on FPStack.
-def : Pat<(X86fpget), (FpGETRESULT)>;
+def FpGETRESULT : FpI_<(ops RFP:$dst), SpecialFP,
+                  [(set RFP:$dst, X86fpget)]>;                    // FPR = ST(0)
 
 let noResults = 1 in 
-  def FpSETRESULT : FpI<(ops RFP:$src), SpecialFP,
-                        []>, Imp<[], [ST0]>;              // ST(0) = FPR
+  def FpSETRESULT : FpI_<(ops RFP:$src), SpecialFP,
+                        [(X86fpset RFP:$src)]>, Imp<[], [ST0]>;   // ST(0) = FPR
+
+// FpI - Floating Point Psuedo Instruction template. Predicated on FPStack.
+class FpI<dag ops, FPFormat fp, list<dag> pattern> :
+  FpI_<ops, fp, pattern>, Requires<[FPStack]>;
 
-// Do not inline into instruction def. since it isn't predicated on FPStack.
-def : Pat<(X86fpset RFP:$src), (FpSETRESULT RFP:$src)>;
 
 def FpMOV       : FpI<(ops RFP:$dst, RFP:$src), SpecialFP, []>; // f1 = fmov f2
 
@@ -2754,18 +2726,11 @@ def FpILD32m : FpI<(ops RFP:$dst, i32mem:$src), ZeroArgFP,
 def FpILD64m : FpI<(ops RFP:$dst, i64mem:$src), ZeroArgFP,
                    []>;
 
-// Required for RET of f32 / f64 values.
-def : Pat<(X86fld addr:$src, f32), (FpLD32m addr:$src)>;
-def : Pat<(X86fld addr:$src, f64), (FpLD64m addr:$src)>;
-
 def FpST32m   : FpI<(ops f32mem:$op, RFP:$src), OneArgFP,
                 [(truncstore RFP:$src, addr:$op, f32)]>;
 def FpST64m   : FpI<(ops f64mem:$op, RFP:$src), OneArgFP,
                 [(store RFP:$src, addr:$op)]>;
 
-def : Pat<(X86fst RFP:$src, addr:$op, f32), (FpST32m addr:$op, RFP:$src)>;
-def : Pat<(X86fst RFP:$src, addr:$op, f64), (FpST64m addr:$op, RFP:$src)>;
-
 def FpSTP32m  : FpI<(ops f32mem:$op, RFP:$src), OneArgFP, []>;
 def FpSTP64m  : FpI<(ops f64mem:$op, RFP:$src), OneArgFP, []>;
 def FpIST16m  : FpI<(ops i16mem:$op, RFP:$src), OneArgFP, []>;
@@ -2799,9 +2764,6 @@ def FpLD0 : FpI<(ops RFP:$dst), ZeroArgFP,
 def FpLD1 : FpI<(ops RFP:$dst), ZeroArgFP,
                 [(set RFP:$dst, fp64imm1)]>;
 
-def : Pat<(f64 fp64immneg0), (FpCHS (FpLD0))>, Requires<[FPStack]>;
-def : Pat<(f64 fp64immneg1), (FpCHS (FpLD1))>, Requires<[FPStack]>;
-
 def FLD0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9;
 def FLD1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9;
 
@@ -2848,6 +2810,68 @@ def FLDCW16m  : I<0xD9, MRM5m,                   // X87 control world = [mem16]
 def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", [(X86rdtsc)]>,
             TB, Imp<[],[EAX,EDX]>;
 
+
+//===----------------------------------------------------------------------===//
+// Non-Instruction Patterns
+//===----------------------------------------------------------------------===//
+
+// Calls
+def : Pat<(X86call tglobaladdr:$dst),
+          (CALLpcrel32 tglobaladdr:$dst)>;
+def : Pat<(X86call externalsym:$dst),
+          (CALLpcrel32 externalsym:$dst)>;
+
+// X86 specific add which produces a flag.
+def : Pat<(X86addflag R32:$src1, R32:$src2),
+          (ADD32rr R32:$src1, R32:$src2)>;
+def : Pat<(X86addflag R32:$src1, (load addr:$src2)),
+          (ADD32rm R32:$src1, addr:$src2)>;
+def : Pat<(X86addflag R32:$src1, imm:$src2),
+          (ADD32ri R32:$src1, imm:$src2)>;
+def : Pat<(X86addflag R32:$src1, i32immSExt8:$src2),
+          (ADD32ri8 R32:$src1, i32immSExt8:$src2)>;
+
+def : Pat<(X86subflag R32:$src1, R32:$src2),
+          (SUB32rr R32:$src1, R32:$src2)>;
+def : Pat<(X86subflag R32:$src1, (load addr:$src2)),
+          (SUB32rm R32:$src1, addr:$src2)>;
+def : Pat<(X86subflag R32:$src1, imm:$src2),
+          (SUB32ri R32:$src1, imm:$src2)>;
+def : Pat<(X86subflag R32:$src1, i32immSExt8:$src2),
+          (SUB32ri8 R32:$src1, i32immSExt8:$src2)>;
+
+// {s|z}extload bool -> {s|z}extload byte
+def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>;
+def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>;
+def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
+def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
+
+// extload bool -> extload byte
+def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
+
+// anyext -> zext
+def : Pat<(i16 (anyext R8 :$src)), (MOVZX16rr8  R8 :$src)>;
+def : Pat<(i32 (anyext R8 :$src)), (MOVZX32rr8  R8 :$src)>;
+def : Pat<(i32 (anyext R16:$src)), (MOVZX32rr16 R16:$src)>;
+
+// Required for RET of f32 / f64 values.
+def : Pat<(X86fld addr:$src, f32), (FpLD32m addr:$src)>;
+def : Pat<(X86fld addr:$src, f64), (FpLD64m addr:$src)>;
+
+// Required for CALL which return f32 / f64 values.
+def : Pat<(X86fst RFP:$src, addr:$op, f32), (FpST32m addr:$op, RFP:$src)>;
+def : Pat<(X86fst RFP:$src, addr:$op, f64), (FpST64m addr:$op, RFP:$src)>;
+
+// Floatin point constant -0.0 and -1.0
+def : Pat<(f64 fp64immneg0), (FpCHS (FpLD0))>, Requires<[FPStack]>;
+def : Pat<(f64 fp64immneg1), (FpCHS (FpLD1))>, Requires<[FPStack]>;
+
+// FR64 undef
+def : Pat<(f64 (undef)), (FLD0SD)>, Requires<[HasSSE2]>;
+// RFP undef
+def : Pat<(f64 (undef)), (FpLD0)>,  Requires<[FPStack]>;
+
+
 //===----------------------------------------------------------------------===//
 // Some peepholes
 //===----------------------------------------------------------------------===//