1.gpu afbc default in yuv color;
2.mb width and hight is equal to xvir and yvir.
Change-Id: I905d90c8a75c0b5136ff883fbcf7128ca954e425
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
return 0;
}
- win->area[0].fbdc_mb_width = win->area[0].xact;
+ win->area[0].fbdc_mb_width = win->area[0].xvir;
win->area[0].fbdc_mb_height = win->area[0].yact;
win->area[0].fbdc_cor_en = 0; /* hreg_block_split */
- win->area[0].fbdc_fmt_cfg |= 0 << 4;
+ win->area[0].fbdc_fmt_cfg |= AFBDC_YUV_COLOR_TRANSFORM << 4;
return 0;
}
#define OUT_CCIR656_MODE_1 6
#define OUT_CCIR656_MODE_2 7
+#define AFBDC_RGB_COLOR_TRANSFORM 0
+#define AFBDC_YUV_COLOR_TRANSFORM 1
+
enum cabc_stage_mode {
LAST_FRAME_PWM_VAL = 0x0,
CUR_FRAME_PWM_VAL = 0x1,