clk: rockchip: rk3368 add 1296000 support to freq table

Change-Id: I6cff0d8820401c36c98f54a9777629dc1d37fba8
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 89ce5a5fdd43664323dcc9057392459a2c7411e6..65dbc9af1af904d01063984b871c064f71af9ff6 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -228,6 +228,7 @@ static struct rockchip_cpuclk_rate_table rk3368_cpuclkb_rates[] __initdata = {
        RK3368_CPUCLKB_RATE(1512000000, 1, 5, 5),
        RK3368_CPUCLKB_RATE(1488000000, 1, 4, 4),
        RK3368_CPUCLKB_RATE(1416000000, 1, 4, 4),
+       RK3368_CPUCLKL_RATE(1296000000, 1, 4, 4),
        RK3368_CPUCLKB_RATE(1200000000, 1, 3, 3),
        RK3368_CPUCLKB_RATE(1008000000, 1, 3, 3),
        RK3368_CPUCLKB_RATE( 816000000, 1, 2, 2),
@@ -241,6 +242,7 @@ static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = {
        RK3368_CPUCLKL_RATE(1512000000, 1, 6, 6),
        RK3368_CPUCLKL_RATE(1488000000, 1, 5, 5),
        RK3368_CPUCLKL_RATE(1416000000, 1, 5, 5),
+       RK3368_CPUCLKL_RATE(1296000000, 1, 5, 5),
        RK3368_CPUCLKL_RATE(1200000000, 1, 4, 4),
        RK3368_CPUCLKL_RATE(1008000000, 1, 4, 4),
        RK3368_CPUCLKL_RATE( 816000000, 1, 3, 3),