Add 8-bit insts. zext behaviour is not modelled yet

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70722 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/MSP430/MSP430InstrInfo.cpp b/lib/Target/MSP430/MSP430InstrInfo.cpp
index c84c96e6569f6887159ecb5a42f9ddaa25550eca..579da6e90eac55ac8483c188a4762c91d765ad7f 100644 (file)
--- a/lib/Target/MSP430/MSP430InstrInfo.cpp
+++ b/lib/Target/MSP430/MSP430InstrInfo.cpp
@@ -32,16 +32,24 @@ bool MSP430InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
                                    unsigned DestReg, unsigned SrcReg,
                                    const TargetRegisterClass *DestRC,
                                    const TargetRegisterClass *SrcRC) const {
-  if (DestRC != SrcRC) {
-    // Not yet supported!
-    return false;
-  }
-
   DebugLoc DL = DebugLoc::getUnknownLoc();
   if (I != MBB.end()) DL = I->getDebugLoc();
 
-  BuildMI(MBB, I, DL, get(MSP430::MOV16rr), DestReg).addReg(SrcReg);
-  return true;
+  if (DestRC == SrcRC) {
+    unsigned Opc;
+    if (DestRC == &MSP430::GR16RegClass) {
+      Opc = MSP430::MOV16rr;
+    } else if (DestRC == &MSP430::GR8RegClass) {
+      Opc = MSP430::MOV8rr;
+    } else {
+      return false;
+    }
+
+    BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg);
+    return true;
+  }
+
+  return false;
 }
 
 bool
@@ -53,8 +61,9 @@ MSP430InstrInfo::isMoveInstr(const MachineInstr& MI,
   switch (MI.getOpcode()) {
   default:
     return false;
+  case MSP430::MOV8rr:
   case MSP430::MOV16rr:
-    assert(MI.getNumOperands() >= 2 &&
+   assert(MI.getNumOperands() >= 2 &&
            MI.getOperand(0).isReg() &&
            MI.getOperand(1).isReg() &&
            "invalid register-register move instruction");

diff --git a/lib/Target/MSP430/MSP430InstrInfo.td b/lib/Target/MSP430/MSP430InstrInfo.td
index d8c06267a73b9ea75e7cfffb89aaf0cc8ec2f2b5..44e3925531f721e3156b43c6d6a1d73250514fab 100644 (file)
--- a/lib/Target/MSP430/MSP430InstrInfo.td
+++ b/lib/Target/MSP430/MSP430InstrInfo.td
@@ -55,6 +55,9 @@ let neverHasSideEffects = 1 in {
 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
                      "mov.w\t{$src, $dst|$dst, $src}",
                      []>;
+def MOV8rr  : Pseudo<(outs GR8:$dst), (ins GR8:$src),
+                     "mov.b\t{$src, $dst|$dst, $src}",
+                     []>;
 }
 
 // FIXME: Provide proper encoding!
@@ -62,6 +65,10 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
                      "mov.w\t{$src, $dst|$dst, $src}",
                      [(set GR16:$dst, imm:$src)]>;
+def MOV8ri  : Pseudo<(outs GR8:$dst), (ins i8imm:$src),
+                     "mov.b\t{$src, $dst|$dst, $src}",
+                     [(set GR8:$dst, imm:$src)]>;
+
 }
 
 //===----------------------------------------------------------------------===//
@@ -77,12 +84,21 @@ def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
                      "add.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
                       (implicit SRW)]>;
+
+def ADD8rr  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
+                     "add.b\t{$src2, $dst|$dst, $src2}",
+                     [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
+                      (implicit SRW)]>;
 }
 
 def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
                      "add.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
                       (implicit SRW)]>;
+def ADD8ri  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
+                     "add.b\t{$src2, $dst|$dst, $src2}",
+                     [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
+                      (implicit SRW)]>;
 
 let Uses = [SRW] in {
 
@@ -91,12 +107,20 @@ def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
                      "addc.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
                       (implicit SRW)]>;
+def ADC8rr  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
+                     "addc.b\t{$src2, $dst|$dst, $src2}",
+                     [(set GR8:$dst, (adde GR8:$src1, GR8:$src2)),
+                      (implicit SRW)]>;
 } // isCommutable
 
 def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
                      "addc.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
                       (implicit SRW)]>;
+def ADC8ri  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
+                     "addc.b\t{$src2, $dst|$dst, $src2}",
+                     [(set GR8:$dst, (adde GR8:$src1, imm:$src2)),
+                      (implicit SRW)]>;
 }
 
 let isCommutable = 1 in { // X = AND Y, Z  == X = AND Z, Y
@@ -104,46 +128,78 @@ def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
                      "and.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
                       (implicit SRW)]>;
+def AND8rr  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
+                     "and.b\t{$src2, $dst|$dst, $src2}",
+                     [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
+                      (implicit SRW)]>;
 }
 
 def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
                      "and.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
                       (implicit SRW)]>;
+def AND8ri  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
+                     "and.b\t{$src2, $dst|$dst, $src2}",
+                     [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
+                      (implicit SRW)]>;
 
 let isCommutable = 1 in { // X = XOR Y, Z  == X = XOR Z, Y
 def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
                      "xor.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
                       (implicit SRW)]>;
+def XOR8rr  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
+                     "xor.b\t{$src2, $dst|$dst, $src2}",
+                     [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
+                      (implicit SRW)]>;
 }
 
 def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
                      "xor.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
                       (implicit SRW)]>;
+def XOR8ri  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
+                     "xor.b\t{$src2, $dst|$dst, $src2}",
+                     [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
+                      (implicit SRW)]>;
 
 
 def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
                      "sub.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
                       (implicit SRW)]>;
+def SUB8rr  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
+                     "sub.b\t{$src2, $dst|$dst, $src2}",
+                     [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
+                      (implicit SRW)]>;
 
 def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
                      "sub.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
                       (implicit SRW)]>;
+def SUB8ri  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
+                     "sub.b\t{$src2, $dst|$dst, $src2}",
+                     [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
+                      (implicit SRW)]>;
 
 let Uses = [SRW] in {
 def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
                      "subc.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
                       (implicit SRW)]>;
+def SBC8rr  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
+                     "subc.b\t{$src2, $dst|$dst, $src2}",
+                     [(set GR8:$dst, (sube GR8:$src1, GR8:$src2)),
+                      (implicit SRW)]>;
 
 def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
                      "subc.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
                       (implicit SRW)]>;
+def SBC8ri  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
+                     "subc.b\t{$src2, $dst|$dst, $src2}",
+                     [(set GR8:$dst, (sube GR8:$src1, imm:$src2)),
+                      (implicit SRW)]>;
 }
 
 // FIXME: Provide proper encoding!
@@ -163,10 +219,16 @@ let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
 def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
                     "bis.w\t{$src2, $dst|$dst, $src2}",
                     [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
+def OR8rr  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
+                    "bis.b\t{$src2, $dst|$dst, $src2}",
+                    [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
 }
 
 def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
                     "bis.w\t{$src2, $dst|$dst, $src2}",
                     [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
+def OR8ri  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
+                    "bis.b\t{$src2, $dst|$dst, $src2}",
+                    [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
 
 } // isTwoAddress = 1