Rename MVT::getVectorBaseType to MVT::getVectorElementType.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37579 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/ValueTypes.h b/include/llvm/CodeGen/ValueTypes.h
index 6f864d79146ff5f92ebddfed00c941e6a97bb5e9..a42cee181b964694ae50ea4e9dddf410c89046f1 100644 (file)
--- a/include/llvm/CodeGen/ValueTypes.h
+++ b/include/llvm/CodeGen/ValueTypes.h
@@ -129,9 +129,9 @@ namespace MVT {  // MVT = Machine Value Types
   ///
   ValueType getVectorType(ValueType VT, unsigned NumElements);
     
-  /// MVT::getVectorBaseType - Given a packed vector type, return the type of
+  /// MVT::getVectorElementType - Given a packed vector type, return the type of
   /// each element.
-  static inline ValueType getVectorBaseType(ValueType VT) {
+  static inline ValueType getVectorElementType(ValueType VT) {
     switch (VT) {
     default: assert(0 && "Invalid vector type!");
     case v8i8 :

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 1dac2ca1ef8b84950d0eba719e7cddee0350051a..8cc4036347943ad73b5235a3200e5273489eb9ca 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1809,7 +1809,7 @@ SDOperand DAGCombiner::visitXOR(SDNode *N) {
       return DAG.getConstant(0, VT);
     } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
       // Produce a vector of zeros.
-      SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
+      SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT));
       std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
       return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
     }

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index aeb6f276c5fb22b5111e151e7b497bc3c9e96272..7d57c00c14169dae55b69d842edafac10bee5ed1 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1014,7 +1014,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         
         unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
         MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
-        MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
+        MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
         
         // We generate a shuffle of InVec and ScVec, so the shuffle mask should
         // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
@@ -1110,7 +1110,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       // FALLTHROUGH
     case TargetLowering::Expand: {
       MVT::ValueType VT = Node->getValueType(0);
-      MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
+      MVT::ValueType EltVT = MVT::getVectorElementType(VT);
       MVT::ValueType PtrVT = TLI.getPointerTy();
       SDOperand Mask = Node->getOperand(2);
       unsigned NumElems = Mask.getNumOperands();
@@ -2386,7 +2386,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
              "Cannot expand this binary operator!");
       // Expand the operation into a bunch of nasty scalar code.
       SmallVector<SDOperand, 8> Ops;
-      MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
+      MVT::ValueType EltVT = MVT::getVectorElementType(Node->getValueType(0));
       MVT::ValueType PtrVT = TLI.getPointerTy();
       for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
            i != e; ++i) {
@@ -4006,7 +4006,7 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
     // Build the shuffle constant vector: <0, 0, 0, 0>
     MVT::ValueType MaskVT = 
       MVT::getIntVectorWithNumElements(NumElems);
-    SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
+    SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
     std::vector<SDOperand> ZeroVec(NumElems, Zero);
     SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
                                       &ZeroVec[0], ZeroVec.size());
@@ -4036,7 +4036,7 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
            E = Values.end(); I != E; ++I) {
       for (std::vector<unsigned>::iterator II = I->second.begin(),
              EE = I->second.end(); II != EE; ++II)
-        MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
+        MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
       i += NumElems;
     }
     SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index e3ee9fb0d8c293465bf479a718e828f3503a0c9c..5c24b931e1717a4bcd4f2c9c3cd169bf00b395ef 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1114,7 +1114,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
     break;
   case ISD::SCALAR_TO_VECTOR:
     assert(MVT::isVector(VT) && !MVT::isVector(Operand.getValueType()) &&
-           MVT::getVectorBaseType(VT) == Operand.getValueType() &&
+           MVT::getVectorElementType(VT) == Operand.getValueType() &&
            "Illegal SCALAR_TO_VECTOR node!");
     break;
   case ISD::FNEG:
@@ -1593,7 +1593,7 @@ SDOperand SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT::ValueType VT,
     ExtType = ISD::NON_EXTLOAD;
 
   if (MVT::isVector(VT))
-    assert(EVT == MVT::getVectorBaseType(VT) && "Invalid vector extload!");
+    assert(EVT == MVT::getVectorElementType(VT) && "Invalid vector extload!");
   else
     assert(EVT < VT && "Should only be an extending load, not truncating!");
   assert((ExtType == ISD::EXTLOAD || MVT::isInteger(VT)) &&

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 69d51d81c2365e1fb0ea1d9e43c63fbb013a2585..ed833e26efdca221bb7f329fdafcf70f5b8e21b6 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -793,7 +793,7 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) {
     
     if (MVT::isVector(PTyElementVT)) {
       Ops.push_back(DAG.getConstant(NE * MVT::getVectorNumElements(PTyElementVT), MVT::i32));
-      Ops.push_back(DAG.getValueType(MVT::getVectorBaseType(PTyElementVT)));
+      Ops.push_back(DAG.getValueType(MVT::getVectorElementType(PTyElementVT)));
       N = DAG.getNode(ISD::VCONCAT_VECTORS, MVT::Vector, &Ops[0], Ops.size());
     } else {
       Ops.push_back(DAG.getConstant(NE, MVT::i32));
@@ -2905,7 +2905,7 @@ SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
     return DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Val, 
                        DAG.getConstant(MVT::getVectorNumElements(RegVT),
                                        MVT::i32),
-                       DAG.getValueType(MVT::getVectorBaseType(RegVT)));
+                       DAG.getValueType(MVT::getVectorElementType(RegVT)));
   }
   
   if (MVT::isInteger(RegVT)) {

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 9723c7c8c2aff09ccbeb74a0aaacddedc0957e0c..edf4294c7a3f99ebd33761eff9c37c6c75de2082 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -2257,7 +2257,7 @@ static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
   MVT::ValueType CanonicalVT = VTys[SplatSize-1];
   
   // Build a canonical splat for this value.
-  SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT));
+  SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT));
   SmallVector<SDOperand, 8> Ops;
   Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
   SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
@@ -2647,7 +2647,7 @@ static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
   
   // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
   // that it is in input element units, not in bytes.  Convert now.
-  MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
+  MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType());
   unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
   
   SmallVector<SDOperand, 16> ResultMask;

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index c1416d2c1f40c9c2dac548d6b49659cce1473fd3..f8b6cea7c061c7b9898daccc0498338305f1b54a 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -2106,7 +2106,7 @@ static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
                                       SelectionDAG &DAG) {
   MVT::ValueType VT = Op.getValueType();
   MVT::ValueType MaskVT = Mask.getValueType();
-  MVT::ValueType EltVT = MVT::getVectorBaseType(MaskVT);
+  MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
   unsigned NumElems = Mask.getNumOperands();
   SmallVector<SDOperand, 8> MaskVec;
 
@@ -2265,7 +2265,7 @@ static bool isZeroShuffle(SDNode *N) {
 static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
   assert(MVT::isVector(VT) && "Expected a vector type");
   unsigned NumElems = MVT::getVectorNumElements(VT);
-  MVT::ValueType EVT = MVT::getVectorBaseType(VT);
+  MVT::ValueType EVT = MVT::getVectorElementType(VT);
   bool isFP = MVT::isFloatingPoint(EVT);
   SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT);
   SmallVector<SDOperand, 8> ZeroVec(NumElems, Zero);
@@ -2302,7 +2302,7 @@ static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
 /// operation of specified width.
 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
   MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
-  MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
+  MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
 
   SmallVector<SDOperand, 8> MaskVec;
   MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
@@ -2315,7 +2315,7 @@ static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
 /// of specified width.
 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
   MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
-  MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
+  MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
   SmallVector<SDOperand, 8> MaskVec;
   for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
     MaskVec.push_back(DAG.getConstant(i,            BaseVT));
@@ -2328,7 +2328,7 @@ static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
 /// of specified width.
 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
   MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
-  MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
+  MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
   unsigned Half = NumElems/2;
   SmallVector<SDOperand, 8> MaskVec;
   for (unsigned i = 0; i != Half; ++i) {
@@ -2366,7 +2366,7 @@ static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
                                              bool isZero, SelectionDAG &DAG) {
   SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
   MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
-  MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
+  MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
   SDOperand Zero = DAG.getConstant(0, EVT);
   SmallVector<SDOperand, 8> MaskVec(NumElems, Zero);
   MaskVec[Idx] = DAG.getConstant(NumElems, EVT);
@@ -2458,7 +2458,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
     return Op;
 
   MVT::ValueType VT = Op.getValueType();
-  MVT::ValueType EVT = MVT::getVectorBaseType(VT);
+  MVT::ValueType EVT = MVT::getVectorElementType(VT);
   unsigned EVTBits = MVT::getSizeInBits(EVT);
 
   unsigned NumElems = Op.getNumOperands();
@@ -2502,7 +2502,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
       Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
                                          DAG);
       MVT::ValueType MaskVT  = MVT::getIntVectorWithNumElements(NumElems);
-      MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
+      MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
       SmallVector<SDOperand, 8> MaskVec;
       for (unsigned i = 0; i < NumElems; i++)
         MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
@@ -2571,7 +2571,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
     if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
       return V[0];
     MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
-    MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
+    MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
     SmallVector<SDOperand, 8> MaskVec;
     bool Reverse = (NonZeros & 0x3) == 2;
     for (unsigned i = 0; i < 2; ++i)
@@ -2728,7 +2728,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
     // Handle v8i16 shuffle high / low shuffle node pair.
     if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
       MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
-      MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
+      MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
       SmallVector<SDOperand, 8> MaskVec;
       for (unsigned i = 0; i != 4; ++i)
         MaskVec.push_back(PermMask.getOperand(i));
@@ -2763,7 +2763,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
       // Don't do this for MMX.
       MVT::getSizeInBits(VT) != 64) {
     MVT::ValueType MaskVT = PermMask.getValueType();
-    MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
+    MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
     SmallVector<std::pair<int, int>, 8> Locs;
     Locs.reserve(NumElems);
     SmallVector<SDOperand, 8> Mask1(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
@@ -2888,10 +2888,10 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
     // SHUFPS the element to the lowest double word, then movss.
     MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
     SmallVector<SDOperand, 8> IdxVec;
-    IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorBaseType(MaskVT)));
-    IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
-    IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
-    IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
+    IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorElementType(MaskVT)));
+    IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
+    IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
+    IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
     SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
                                  &IdxVec[0], IdxVec.size());
     Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
@@ -2909,8 +2909,8 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
     // to a f64mem, the whole operation is folded into a single MOVHPDmr.
     MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
     SmallVector<SDOperand, 8> IdxVec;
-    IdxVec.push_back(DAG.getConstant(1, MVT::getVectorBaseType(MaskVT)));
-    IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
+    IdxVec.push_back(DAG.getConstant(1, MVT::getVectorElementType(MaskVT)));
+    IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
     SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
                                  &IdxVec[0], IdxVec.size());
     Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
@@ -2927,7 +2927,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
   // Transform it so it match pinsrw which expects a 16-bit value in a GR32
   // as its second argument.
   MVT::ValueType VT = Op.getValueType();
-  MVT::ValueType BaseVT = MVT::getVectorBaseType(VT);
+  MVT::ValueType BaseVT = MVT::getVectorElementType(VT);
   SDOperand N0 = Op.getOperand(0);
   SDOperand N1 = Op.getOperand(1);
   SDOperand N2 = Op.getOperand(2);
@@ -2943,7 +2943,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
       // Use a movss.
       N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1);
       MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
-      MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
+      MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
       SmallVector<SDOperand, 8> MaskVec;
       MaskVec.push_back(DAG.getConstant(4, BaseVT));
       for (unsigned i = 1; i <= 3; ++i)
@@ -4513,11 +4513,11 @@ static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
   i %= NumElems;
   if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) {
     return (i == 0)
-      ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT));
+      ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
   } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) {
     SDOperand Idx = PermMask.getOperand(i);
     if (Idx.getOpcode() == ISD::UNDEF)
-      return DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT));
+      return DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
     return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG);
   }
   return SDOperand();
@@ -4613,7 +4613,7 @@ static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
   MachineFunction &MF = DAG.getMachineFunction();
   MachineFrameInfo *MFI = MF.getFrameInfo();
   MVT::ValueType VT = N->getValueType(0);
-  MVT::ValueType EVT = MVT::getVectorBaseType(VT);
+  MVT::ValueType EVT = MVT::getVectorElementType(VT);
   SDOperand PermMask = N->getOperand(2);
   int NumElems = (int)PermMask.getNumOperands();
   SDNode *Base = NULL;