+++ /dev/null
-//===--- HexagonCExttable.h - Instruction constant extender table info. ---===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-// HexagonCExt table maps the constant extended form of an instruction to
-// the non-extended form. In addition, it also contains other information,
-// such as the extended operand number and their min/max values.
-//===----------------------------------------------------------------------===//
-
-#ifndef HEXAGONCEXTTABLE_H
-#define HEXAGONCEXTTABLE_H
-
- const HexagonConstExtInfo HexagonCExt[] = {
- { "PHI", -1, 0, 0, -1},
- { "INLINEASM", -1, 0, 0, -1},
- { "PROLOG_LABEL", -1, 0, 0, -1},
- { "EH_LABEL", -1, 0, 0, -1},
- { "GC_LABEL", -1, 0, 0, -1},
- { "KILL", -1, 0, 0, -1},
- { "EXTRACT_SUBREG", -1, 0, 0, -1},
- { "INSERT_SUBREG", -1, 0, 0, -1},
- { "IMPLICIT_DEF", -1, 0, 0, -1},
- { "SUBREG_TO_REG", -1, 0, 0, -1},
- { "COPY_TO_REGCLASS", -1, 0, 0, -1},
- { "DBG_VALUE", -1, 0, 0, -1},
- { "REG_SEQUENCE", -1, 0, 0, -1},
- { "COPY", -1, 0, 0, -1},
- { "BUNDLE", -1, 0, 0, -1},
- { "ADD64_rr", -1, 0, 0, -1},
- { "ADDASL", -1, 0, 0, -1},
- { "ADD_ri", 2, -32768, 32767, Hexagon::ADD_rr},
- { "ADD_ri_cNotPt", 3, -128, 127, Hexagon::ADD_rr_cNotPt},
- { "ADD_ri_cPt", 3, -128, 127, Hexagon::ADD_rr_cPt},
- { "ADD_ri_cdnNotPt", 3, -128, 127, Hexagon::ADD_rr_cdnNotPt},
- { "ADD_ri_cdnPt", 3, -128, 127, Hexagon::ADD_rr_cdnPt},
- { "ADD_rr", -1, 0, 0, -1},
- { "ADD_rr_cNotPt", -1, 0, 0, -1},
- { "ADD_rr_cPt", -1, 0, 0, -1},
- { "ADD_rr_cdnNotPt", -1, 0, 0, -1},
- { "ADD_rr_cdnPt", -1, 0, 0, -1},
- { "ADDi_ASLri_V4", 1, 0, 255, -1},
- { "ADDi_LSRri_V4", 1, 0, 255, -1},
- { "ADDi_MPYri_V4", 1, 0, 63, -1},
- { "ADDi_MPYrr_V4", 1, 0, 63, Hexagon::ADDr_MPYrr_V4},
- { "ADDr_ADDri_V4", 3, -32, 31, -1},
- { "ADDr_MPYir_V4", -1, 0, 0, -1},
- { "ADDr_MPYri_V4", 3, 0, 63, Hexagon::ADDr_MPYrr_V4},
- { "ADDr_MPYrr_V4", -1, 0, 0, -1},
- { "ADDr_SUBri_V4", 2, -32, 31, -1},
- { "ADDri_SUBr_V4", 2, -32, 31, -1},
- { "ADDri_acc", 3, -128, 127, Hexagon::ADDrr_acc},
- { "ADDrr_acc", -1, 0, 0, -1},
- { "ADJCALLSTACKDOWN", -1, 0, 0, -1},
- { "ADJCALLSTACKUP", -1, 0, 0, -1},
- { "ADJDYNALLOC", -1, 0, 0, -1},
- { "ALLOCFRAME", -1, 0, 0, -1},
- { "ALL_pp", -1, 0, 0, -1},
- { "AND_pnotp", -1, 0, 0, -1},
- { "AND_pp", -1, 0, 0, -1},
- { "AND_ri", 2, -512, 511, Hexagon::AND_rr},
- { "AND_rr", -1, 0, 0, -1},
- { "AND_rr64", -1, 0, 0, -1},
- { "AND_rr_cNotPt", -1, 0, 0, -1},
- { "AND_rr_cPt", -1, 0, 0, -1},
- { "AND_rr_cdnNotPt", -1, 0, 0, -1},
- { "AND_rr_cdnPt", -1, 0, 0, -1},
- { "ANDd_NOTd_V4", -1, 0, 0, -1},
- { "ANDi_ASLri_V4", 1, 0, 255, -1},
- { "ANDi_LSRri_V4", 1, 0, 255, -1},
- { "ANDr_ANDr_NOTr_V4", -1, 0, 0, -1},
- { "ANDr_ANDrr_V4", -1, 0, 0, -1},
- { "ANDr_ORrr_V4", -1, 0, 0, -1},
- { "ANDr_XORrr_V4", -1, 0, 0, -1},
- { "ANY_pp", -1, 0, 0, -1},
- { "ARGEXTEND", -1, 0, 0, -1},
- { "ASL", -1, 0, 0, -1},
- { "ASLH", -1, 0, 0, -1},
- { "ASLH_cNotPt_V4", -1, 0, 0, -1},
- { "ASLH_cPt_V4", -1, 0, 0, -1},
- { "ASLH_cdnNotPt_V4", -1, 0, 0, -1},
- { "ASLH_cdnPt_V4", -1, 0, 0, -1},
- { "ASL_ADD_ri", -1, 0, 0, -1},
- { "ASL_ADD_rr", -1, 0, 0, -1},
- { "ASL_ADDd_ri", -1, 0, 0, -1},
- { "ASL_ADDd_rr", -1, 0, 0, -1},
- { "ASL_AND_ri", -1, 0, 0, -1},
- { "ASL_AND_rr", -1, 0, 0, -1},
- { "ASL_ANDd_ri", -1, 0, 0, -1},
- { "ASL_ANDd_rr", -1, 0, 0, -1},
- { "ASL_OR_ri", -1, 0, 0, -1},
- { "ASL_OR_rr", -1, 0, 0, -1},
- { "ASL_ORd_ri", -1, 0, 0, -1},
- { "ASL_ORd_rr", -1, 0, 0, -1},
- { "ASL_SUB_ri", -1, 0, 0, -1},
- { "ASL_SUB_rr", -1, 0, 0, -1},
- { "ASL_SUBd_ri", -1, 0, 0, -1},
- { "ASL_SUBd_rr", -1, 0, 0, -1},
- { "ASL_XOR_ri", -1, 0, 0, -1},
- { "ASL_XORd_ri", -1, 0, 0, -1},
- { "ASL_rr", -1, 0, 0, -1},
- { "ASLd", -1, 0, 0, -1},
- { "ASLd_ri", -1, 0, 0, -1},
- { "ASLd_rr_xor_V4", -1, 0, 0, -1},
- { "ASRH", -1, 0, 0, -1},
- { "ASRH_cNotPt_V4", -1, 0, 0, -1},
- { "ASRH_cPt_V4", -1, 0, 0, -1},
- { "ASRH_cdnNotPt_V4", -1, 0, 0, -1},
- { "ASRH_cdnPt_V4", -1, 0, 0, -1},
- { "ASR_ADD_ri", -1, 0, 0, -1},
- { "ASR_ADD_rr", -1, 0, 0, -1},
- { "ASR_ADDd_ri", -1, 0, 0, -1},
- { "ASR_ADDd_rr", -1, 0, 0, -1},
- { "ASR_AND_ri", -1, 0, 0, -1},
- { "ASR_AND_rr", -1, 0, 0, -1},
- { "ASR_ANDd_ri", -1, 0, 0, -1},
- { "ASR_ANDd_rr", -1, 0, 0, -1},
- { "ASR_OR_ri", -1, 0, 0, -1},
- { "ASR_OR_rr", -1, 0, 0, -1},
- { "ASR_ORd_ri", -1, 0, 0, -1},
- { "ASR_ORd_rr", -1, 0, 0, -1},
- { "ASR_SUB_ri", -1, 0, 0, -1},
- { "ASR_SUB_rr", -1, 0, 0, -1},
- { "ASR_SUBd_ri", -1, 0, 0, -1},
- { "ASR_SUBd_rr", -1, 0, 0, -1},
- { "ASR_ri", -1, 0, 0, -1},
- { "ASR_rr", -1, 0, 0, -1},
- { "ASRd_ri", -1, 0, 0, -1},
- { "ASRd_rr", -1, 0, 0, -1},
- { "ASRd_rr_xor_V4", -1, 0, 0, -1},
- { "BARRIER", -1, 0, 0, -1},
- { "BRCOND", -1, 0, 0, -1},
- { "BR_JT", -1, 0, 0, -1},
- { "CALL", -1, 0, 0, -1},
- { "CALLR", -1, 0, 0, -1},
- { "CALLRv3", -1, 0, 0, -1},
- { "CALLv3", -1, 0, 0, -1},
- { "CLRBIT", -1, 0, 0, -1},
- { "CLRBIT_31", -1, 0, 0, -1},
- { "CMPEHexagon4rr", -1, 0, 0, -1},
- { "CMPEQri", 2, -512, 511, Hexagon::CMPEQrr},
- { "CMPEQrr", -1, 0, 0, -1},
- { "CMPGEUri", 2, 0, 255, -1},
- { "CMPGEri", 2, -128, 127, -1},
- { "CMPGT64rr", -1, 0, 0, -1},
- { "CMPGTU64rr", -1, 0, 0, -1},
- { "CMPGTUri", 2, 0, 511, Hexagon::CMPGTUrr},
- { "CMPGTUrr", -1, 0, 0, -1},
- { "CMPGTri", 2, -512, 511, Hexagon::CMPGTrr},
- { "CMPGTrr", -1, 0, 0, -1},
- { "CMPLTUrr", -1, 0, 0, -1},
- { "CMPLTrr", -1, 0, 0, -1},
- { "CMPbEQri_V4", -1, 0, 0, -1},
- { "CMPbEQrr_sbsb_V4", -1, 0, 0, -1},
- { "CMPbEQrr_ubub_V4", -1, 0, 0, -1},
- { "CMPbGTUri_V4", 2, 0, 127, Hexagon::CMPbGTUrr_V4},
- { "CMPbGTUrr_V4", -1, 0, 0, -1},
- { "CMPbGTrr_V4", -1, 0, 0, -1},
- { "CMPhEQri_V4", -1, 0, 0, -1},
- { "CMPhEQrr_shl_V4", -1, 0, 0, -1},
- { "CMPhEQrr_xor_V4", -1, 0, 0, -1},
- { "CMPhGTUri_V4", 2, 0, 127, Hexagon::CMPhGTUrr_V4},
- { "CMPhGTUrr_V4", -1, 0, 0, -1},
- { "CMPhGTrr_shl_V4", -1, 0, 0, -1},
- { "COMBINE_ii", -1, 0, 0, -1},
- { "COMBINE_ir_V4", -1, 0, 0, -1},
- { "COMBINE_ri_V4", -1, 0, 0, -1},
- { "COMBINE_rr", -1, 0, 0, -1},
- { "COMBINE_rr_cNotPt", -1, 0, 0, -1},
- { "COMBINE_rr_cPt", -1, 0, 0, -1},
- { "COMBINE_rr_cdnNotPt", -1, 0, 0, -1},
- { "COMBINE_rr_cdnPt", -1, 0, 0, -1},
- { "CONST32", -1, 0, 0, -1},
- { "CONST32GP_set", -1, 0, 0, -1},
- { "CONST32_Float_Real", -1, 0, 0, -1},
- { "CONST32_Int_Real", -1, 0, 0, -1},
- { "CONST32_Label", -1, 0, 0, -1},
- { "CONST32_set", -1, 0, 0, -1},
- { "CONST32_set_jt", -1, 0, 0, -1},
- { "CONST64_Float_Real", -1, 0, 0, -1},
- { "CONST64_Int_Real", -1, 0, 0, -1},
- { "CONVERT_d2df", -1, 0, 0, -1},
- { "CONVERT_d2sf", -1, 0, 0, -1},
- { "CONVERT_df2d", -1, 0, 0, -1},
- { "CONVERT_df2d_nchop", -1, 0, 0, -1},
- { "CONVERT_df2sf", -1, 0, 0, -1},
- { "CONVERT_df2ud", -1, 0, 0, -1},
- { "CONVERT_df2ud_nchop", -1, 0, 0, -1},
- { "CONVERT_df2uw", -1, 0, 0, -1},
- { "CONVERT_df2uw_nchop", -1, 0, 0, -1},
- { "CONVERT_df2w", -1, 0, 0, -1},
- { "CONVERT_df2w_nchop", -1, 0, 0, -1},
- { "CONVERT_sf2d", -1, 0, 0, -1},
- { "CONVERT_sf2d_nchop", -1, 0, 0, -1},
- { "CONVERT_sf2df", -1, 0, 0, -1},
- { "CONVERT_sf2ud", -1, 0, 0, -1},
- { "CONVERT_sf2ud_nchop", -1, 0, 0, -1},
- { "CONVERT_sf2uw", -1, 0, 0, -1},
- { "CONVERT_sf2uw_nchop", -1, 0, 0, -1},
- { "CONVERT_sf2w", -1, 0, 0, -1},
- { "CONVERT_sf2w_nchop", -1, 0, 0, -1},
- { "CONVERT_ud2df", -1, 0, 0, -1},
- { "CONVERT_ud2sf", -1, 0, 0, -1},
- { "CONVERT_uw2df", -1, 0, 0, -1},
- { "CONVERT_uw2sf", -1, 0, 0, -1},
- { "CONVERT_w2df", -1, 0, 0, -1},
- { "CONVERT_w2sf", -1, 0, 0, -1},
- { "DEALLOCFRAME", -1, 0, 0, -1},
- { "DEALLOC_RET_V4", -1, 0, 0, -1},
- { "DEALLOC_RET_cNotPt_V4", -1, 0, 0, -1},
- { "DEALLOC_RET_cNotdnPnt_V4", -1, 0, 0, -1},
- { "DEALLOC_RET_cNotdnPt_V4", -1, 0, 0, -1},
- { "DEALLOC_RET_cPt_V4", -1, 0, 0, -1},
- { "DEALLOC_RET_cdnPnt_V4", -1, 0, 0, -1},
- { "DEALLOC_RET_cdnPt_V4", -1, 0, 0, -1},
- { "ENDLOOP0", -1, 0, 0, -1},
- { "FCMPOEQ32_rr", -1, 0, 0, -1},
- { "FCMPOEQ64_rr", -1, 0, 0, -1},
- { "FCMPOGE32_rr", -1, 0, 0, -1},
- { "FCMPOGE64_rr", -1, 0, 0, -1},
- { "FCMPOGT32_rr", -1, 0, 0, -1},
- { "FCMPOGT64_rr", -1, 0, 0, -1},
- { "FCMPUEQ32_rr", -1, 0, 0, -1},
- { "FCMPUEQ64_rr", -1, 0, 0, -1},
- { "FCMPUGE32_rr", -1, 0, 0, -1},
- { "FCMPUGE64_rr", -1, 0, 0, -1},
- { "FCMPUGT32_rr", -1, 0, 0, -1},
- { "FCMPUGT64_rr", -1, 0, 0, -1},
- { "FCONST32_nsdata", -1, 0, 0, -1},
- { "FMADD_dp", -1, 0, 0, -1},
- { "FMADD_sp", -1, 0, 0, -1},
- { "FMAX_dp", -1, 0, 0, -1},
- { "FMAX_sp", -1, 0, 0, -1},
- { "FMIN_dp", -1, 0, 0, -1},
- { "FMIN_sp", -1, 0, 0, -1},
- { "HEXAGON_A2_abs", -1, 0, 0, -1},
- { "HEXAGON_A2_absp", -1, 0, 0, -1},
- { "HEXAGON_A2_abssat", -1, 0, 0, -1},
- { "HEXAGON_A2_add", -1, 0, 0, -1},
- { "HEXAGON_A2_addh_h16_hh", -1, 0, 0, -1},
- { "HEXAGON_A2_addh_h16_hl", -1, 0, 0, -1},
- { "HEXAGON_A2_addh_h16_lh", -1, 0, 0, -1},
- { "HEXAGON_A2_addh_h16_ll", -1, 0, 0, -1},
- { "HEXAGON_A2_addh_h16_sat_hh", -1, 0, 0, -1},
- { "HEXAGON_A2_addh_h16_sat_hl", -1, 0, 0, -1},
- { "HEXAGON_A2_addh_h16_sat_lh", -1, 0, 0, -1},
- { "HEXAGON_A2_addh_h16_sat_ll", -1, 0, 0, -1},
- { "HEXAGON_A2_addh_l16_hl", -1, 0, 0, -1},
- { "HEXAGON_A2_addh_l16_ll", -1, 0, 0, -1},
- { "HEXAGON_A2_addh_l16_sat_hl", -1, 0, 0, -1},
- { "HEXAGON_A2_addh_l16_sat_ll", -1, 0, 0, -1},
- { "HEXAGON_A2_addi", -1, 0, 0, -1},
- { "HEXAGON_A2_addp", -1, 0, 0, -1},
- { "HEXAGON_A2_addsat", -1, 0, 0, -1},
- { "HEXAGON_A2_and", -1, 0, 0, -1},
- { "HEXAGON_A2_andir", -1, 0, 0, -1},
- { "HEXAGON_A2_andp", -1, 0, 0, -1},
- { "HEXAGON_A2_aslh", -1, 0, 0, -1},
- { "HEXAGON_A2_asrh", -1, 0, 0, -1},
- { "HEXAGON_A2_combine_hh", -1, 0, 0, -1},
- { "HEXAGON_A2_combine_hl", -1, 0, 0, -1},
- { "HEXAGON_A2_combine_lh", -1, 0, 0, -1},
- { "HEXAGON_A2_combine_ll", -1, 0, 0, -1},
- { "HEXAGON_A2_combineii", -1, 0, 0, -1},
- { "HEXAGON_A2_combinew", -1, 0, 0, -1},
- { "HEXAGON_A2_max", -1, 0, 0, -1},
- { "HEXAGON_A2_maxu", -1, 0, 0, -1},
- { "HEXAGON_A2_min", -1, 0, 0, -1},
- { "HEXAGON_A2_minu", -1, 0, 0, -1},
- { "HEXAGON_A2_neg", -1, 0, 0, -1},
- { "HEXAGON_A2_negp", -1, 0, 0, -1},
- { "HEXAGON_A2_negsat", -1, 0, 0, -1},
- { "HEXAGON_A2_not", -1, 0, 0, -1},
- { "HEXAGON_A2_notp", -1, 0, 0, -1},
- { "HEXAGON_A2_or", -1, 0, 0, -1},
- { "HEXAGON_A2_orir", -1, 0, 0, -1},
- { "HEXAGON_A2_orp", -1, 0, 0, -1},
- { "HEXAGON_A2_sat", -1, 0, 0, -1},
- { "HEXAGON_A2_satb", -1, 0, 0, -1},
- { "HEXAGON_A2_sath", -1, 0, 0, -1},
- { "HEXAGON_A2_satub", -1, 0, 0, -1},
- { "HEXAGON_A2_satuh", -1, 0, 0, -1},
- { "HEXAGON_A2_sub", -1, 0, 0, -1},
- { "HEXAGON_A2_subh_h16_hh", -1, 0, 0, -1},
- { "HEXAGON_A2_subh_h16_hl", -1, 0, 0, -1},
- { "HEXAGON_A2_subh_h16_lh", -1, 0, 0, -1},
- { "HEXAGON_A2_subh_h16_ll", -1, 0, 0, -1},
- { "HEXAGON_A2_subh_h16_sat_hh", -1, 0, 0, -1},
- { "HEXAGON_A2_subh_h16_sat_hl", -1, 0, 0, -1},
- { "HEXAGON_A2_subh_h16_sat_lh", -1, 0, 0, -1},
- { "HEXAGON_A2_subh_h16_sat_ll", -1, 0, 0, -1},
- { "HEXAGON_A2_subh_l16_hl", -1, 0, 0, -1},
- { "HEXAGON_A2_subh_l16_ll", -1, 0, 0, -1},
- { "HEXAGON_A2_subh_l16_sat_hl", -1, 0, 0, -1},
- { "HEXAGON_A2_subh_l16_sat_ll", -1, 0, 0, -1},
- { "HEXAGON_A2_subp", -1, 0, 0, -1},
- { "HEXAGON_A2_subri", -1, 0, 0, -1},
- { "HEXAGON_A2_subsat", -1, 0, 0, -1},
- { "HEXAGON_A2_svaddh", -1, 0, 0, -1},
- { "HEXAGON_A2_svaddhs", -1, 0, 0, -1},
- { "HEXAGON_A2_svadduhs", -1, 0, 0, -1},
- { "HEXAGON_A2_svavgh", -1, 0, 0, -1},
- { "HEXAGON_A2_svavghs", -1, 0, 0, -1},
- { "HEXAGON_A2_svnavgh", -1, 0, 0, -1},
- { "HEXAGON_A2_svsubh", -1, 0, 0, -1},
- { "HEXAGON_A2_svsubhs", -1, 0, 0, -1},
- { "HEXAGON_A2_svsubuhs", -1, 0, 0, -1},
- { "HEXAGON_A2_swiz", -1, 0, 0, -1},
- { "HEXAGON_A2_sxtb", -1, 0, 0, -1},
- { "HEXAGON_A2_sxth", -1, 0, 0, -1},
- { "HEXAGON_A2_sxtw", -1, 0, 0, -1},
- { "HEXAGON_A2_tfr", -1, 0, 0, -1},
- { "HEXAGON_A2_tfrih", -1, 0, 0, -1},
- { "HEXAGON_A2_tfril", -1, 0, 0, -1},
- { "HEXAGON_A2_tfrp", -1, 0, 0, -1},
- { "HEXAGON_A2_tfrpi", -1, 0, 0, -1},
- { "HEXAGON_A2_tfrsi", -1, 0, 0, -1},
- { "HEXAGON_A2_vabsh", -1, 0, 0, -1},
- { "HEXAGON_A2_vabshsat", -1, 0, 0, -1},
- { "HEXAGON_A2_vabsw", -1, 0, 0, -1},
- { "HEXAGON_A2_vabswsat", -1, 0, 0, -1},
- { "HEXAGON_A2_vaddh", -1, 0, 0, -1},
- { "HEXAGON_A2_vaddhs", -1, 0, 0, -1},
- { "HEXAGON_A2_vaddub", -1, 0, 0, -1},
- { "HEXAGON_A2_vaddubs", -1, 0, 0, -1},
- { "HEXAGON_A2_vadduhs", -1, 0, 0, -1},
- { "HEXAGON_A2_vaddw", -1, 0, 0, -1},
- { "HEXAGON_A2_vaddws", -1, 0, 0, -1},
- { "HEXAGON_A2_vavgh", -1, 0, 0, -1},
- { "HEXAGON_A2_vavghcr", -1, 0, 0, -1},
- { "HEXAGON_A2_vavghr", -1, 0, 0, -1},
- { "HEXAGON_A2_vavgub", -1, 0, 0, -1},
- { "HEXAGON_A2_vavgubr", -1, 0, 0, -1},
- { "HEXAGON_A2_vavguh", -1, 0, 0, -1},
- { "HEXAGON_A2_vavguhr", -1, 0, 0, -1},
- { "HEXAGON_A2_vavguw", -1, 0, 0, -1},
- { "HEXAGON_A2_vavguwr", -1, 0, 0, -1},
- { "HEXAGON_A2_vavgw", -1, 0, 0, -1},
- { "HEXAGON_A2_vavgwcr", -1, 0, 0, -1},
- { "HEXAGON_A2_vavgwr", -1, 0, 0, -1},
- { "HEXAGON_A2_vcmpbeq", -1, 0, 0, -1},
- { "HEXAGON_A2_vcmpbgtu", -1, 0, 0, -1},
- { "HEXAGON_A2_vcmpheq", -1, 0, 0, -1},
- { "HEXAGON_A2_vcmphgt", -1, 0, 0, -1},
- { "HEXAGON_A2_vcmphgtu", -1, 0, 0, -1},
- { "HEXAGON_A2_vcmpweq", -1, 0, 0, -1},
- { "HEXAGON_A2_vcmpwgt", -1, 0, 0, -1},
- { "HEXAGON_A2_vcmpwgtu", -1, 0, 0, -1},
- { "HEXAGON_A2_vconj", -1, 0, 0, -1},
- { "HEXAGON_A2_vmaxh", -1, 0, 0, -1},
- { "HEXAGON_A2_vmaxub", -1, 0, 0, -1},
- { "HEXAGON_A2_vmaxuh", -1, 0, 0, -1},
- { "HEXAGON_A2_vmaxuw", -1, 0, 0, -1},
- { "HEXAGON_A2_vmaxw", -1, 0, 0, -1},
- { "HEXAGON_A2_vminh", -1, 0, 0, -1},
- { "HEXAGON_A2_vminub", -1, 0, 0, -1},
- { "HEXAGON_A2_vminuh", -1, 0, 0, -1},
- { "HEXAGON_A2_vminuw", -1, 0, 0, -1},
- { "HEXAGON_A2_vminw", -1, 0, 0, -1},
- { "HEXAGON_A2_vnavgh", -1, 0, 0, -1},
- { "HEXAGON_A2_vnavghcr", -1, 0, 0, -1},
- { "HEXAGON_A2_vnavghr", -1, 0, 0, -1},
- { "HEXAGON_A2_vnavgw", -1, 0, 0, -1},
- { "HEXAGON_A2_vnavgwcr", -1, 0, 0, -1},
- { "HEXAGON_A2_vnavgwr", -1, 0, 0, -1},
- { "HEXAGON_A2_vraddub", -1, 0, 0, -1},
- { "HEXAGON_A2_vraddub_acc", -1, 0, 0, -1},
- { "HEXAGON_A2_vrsadub", -1, 0, 0, -1},
- { "HEXAGON_A2_vrsadub_acc", -1, 0, 0, -1},
- { "HEXAGON_A2_vsubh", -1, 0, 0, -1},
- { "HEXAGON_A2_vsubhs", -1, 0, 0, -1},
- { "HEXAGON_A2_vsubub", -1, 0, 0, -1},
- { "HEXAGON_A2_vsububs", -1, 0, 0, -1},
- { "HEXAGON_A2_vsubuhs", -1, 0, 0, -1},
- { "HEXAGON_A2_vsubw", -1, 0, 0, -1},
- { "HEXAGON_A2_vsubws", -1, 0, 0, -1},
- { "HEXAGON_A2_xor", -1, 0, 0, -1},
- { "HEXAGON_A2_xorp", -1, 0, 0, -1},
- { "HEXAGON_A2_zxtb", -1, 0, 0, -1},
- { "HEXAGON_A2_zxth", -1, 0, 0, -1},
- { "HEXAGON_A4_cround_ri", -1, 0, 0, -1},
- { "HEXAGON_A4_cround_rr", -1, 0, 0, -1},
- { "HEXAGON_A4_modwrapu", -1, 0, 0, -1},
- { "HEXAGON_A4_round_ri", -1, 0, 0, -1},
- { "HEXAGON_A4_round_ri_sat", -1, 0, 0, -1},
- { "HEXAGON_A4_round_rr", -1, 0, 0, -1},
- { "HEXAGON_A4_round_rr_sat", -1, 0, 0, -1},
- { "HEXAGON_A5_vaddhubs", -1, 0, 0, -1},
- { "HEXAGON_C2_all8", -1, 0, 0, -1},
- { "HEXAGON_C2_and", -1, 0, 0, -1},
- { "HEXAGON_C2_andn", -1, 0, 0, -1},
- { "HEXAGON_C2_any8", -1, 0, 0, -1},
- { "HEXAGON_C2_cmpeq", -1, 0, 0, -1},
- { "HEXAGON_C2_cmpeqi", -1, 0, 0, -1},
- { "HEXAGON_C2_cmpeqp", -1, 0, 0, -1},
- { "HEXAGON_C2_cmpgei", -1, 0, 0, -1},
- { "HEXAGON_C2_cmpgeui", -1, 0, 0, -1},
- { "HEXAGON_C2_cmpgt", -1, 0, 0, -1},
- { "HEXAGON_C2_cmpgti", -1, 0, 0, -1},
- { "HEXAGON_C2_cmpgtp", -1, 0, 0, -1},
- { "HEXAGON_C2_cmpgtu", -1, 0, 0, -1},
- { "HEXAGON_C2_cmpgtui", -1, 0, 0, -1},
- { "HEXAGON_C2_cmpgtup", -1, 0, 0, -1},
- { "HEXAGON_C2_cmplt", -1, 0, 0, -1},
- { "HEXAGON_C2_cmpltu", -1, 0, 0, -1},
- { "HEXAGON_C2_mask", -1, 0, 0, -1},
- { "HEXAGON_C2_mux", -1, 0, 0, -1},
- { "HEXAGON_C2_muxii", -1, 0, 0, -1},
- { "HEXAGON_C2_muxir", -1, 0, 0, -1},
- { "HEXAGON_C2_muxri", -1, 0, 0, -1},
- { "HEXAGON_C2_not", -1, 0, 0, -1},
- { "HEXAGON_C2_or", -1, 0, 0, -1},
- { "HEXAGON_C2_orn", -1, 0, 0, -1},
- { "HEXAGON_C2_pxfer_map", -1, 0, 0, -1},
- { "HEXAGON_C2_tfrpr", -1, 0, 0, -1},
- { "HEXAGON_C2_tfrrp", -1, 0, 0, -1},
- { "HEXAGON_C2_vitpack", -1, 0, 0, -1},
- { "HEXAGON_C2_vmux", -1, 0, 0, -1},
- { "HEXAGON_C2_xor", -1, 0, 0, -1},
- { "HEXAGON_C4_fastcorner9", -1, 0, 0, -1},
- { "HEXAGON_C4_fastcorner9_not", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_d2df", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_d2sf", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_df2d", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_df2d_chop", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_df2sf", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_df2ud", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_df2ud_chop", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_df2uw", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_df2uw_chop", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_df2w", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_df2w_chop", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_sf2d", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_sf2d_chop", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_sf2df", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_sf2ud", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_sf2ud_chop", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_sf2uw", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_sf2uw_chop", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_sf2w", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_sf2w_chop", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_ud2df", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_ud2sf", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_uw2df", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_uw2sf", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_w2df", -1, 0, 0, -1},
- { "HEXAGON_F2_conv_w2sf", -1, 0, 0, -1},
- { "HEXAGON_F2_dfadd", -1, 0, 0, -1},
- { "HEXAGON_F2_dfclass", -1, 0, 0, -1},
- { "HEXAGON_F2_dfcmpeq", -1, 0, 0, -1},
- { "HEXAGON_F2_dfcmpge", -1, 0, 0, -1},
- { "HEXAGON_F2_dfcmpgt", -1, 0, 0, -1},
- { "HEXAGON_F2_dfcmpuo", -1, 0, 0, -1},
- { "HEXAGON_F2_dffixupd", -1, 0, 0, -1},
- { "HEXAGON_F2_dffixupn", -1, 0, 0, -1},
- { "HEXAGON_F2_dffixupr", -1, 0, 0, -1},
- { "HEXAGON_F2_dffma", -1, 0, 0, -1},
- { "HEXAGON_F2_dffma_lib", -1, 0, 0, -1},
- { "HEXAGON_F2_dffma_sc", -1, 0, 0, -1},
- { "HEXAGON_F2_dffms", -1, 0, 0, -1},
- { "HEXAGON_F2_dffms_lib", -1, 0, 0, -1},
- { "HEXAGON_F2_dfimm_n", -1, 0, 0, -1},
- { "HEXAGON_F2_dfimm_p", -1, 0, 0, -1},
- { "HEXAGON_F2_dfmax", -1, 0, 0, -1},
- { "HEXAGON_F2_dfmin", -1, 0, 0, -1},
- { "HEXAGON_F2_dfmpy", -1, 0, 0, -1},
- { "HEXAGON_F2_dfsub", -1, 0, 0, -1},
- { "HEXAGON_F2_sfadd", -1, 0, 0, -1},
- { "HEXAGON_F2_sfclass", -1, 0, 0, -1},
- { "HEXAGON_F2_sfcmpeq", -1, 0, 0, -1},
- { "HEXAGON_F2_sfcmpge", -1, 0, 0, -1},
- { "HEXAGON_F2_sfcmpgt", -1, 0, 0, -1},
- { "HEXAGON_F2_sfcmpuo", -1, 0, 0, -1},
- { "HEXAGON_F2_sffixupd", -1, 0, 0, -1},
- { "HEXAGON_F2_sffixupn", -1, 0, 0, -1},
- { "HEXAGON_F2_sffixupr", -1, 0, 0, -1},
- { "HEXAGON_F2_sffma", -1, 0, 0, -1},
- { "HEXAGON_F2_sffma_lib", -1, 0, 0, -1},
- { "HEXAGON_F2_sffma_sc", -1, 0, 0, -1},
- { "HEXAGON_F2_sffms", -1, 0, 0, -1},
- { "HEXAGON_F2_sffms_lib", -1, 0, 0, -1},
- { "HEXAGON_F2_sfimm_n", -1, 0, 0, -1},
- { "HEXAGON_F2_sfimm_p", -1, 0, 0, -1},
- { "HEXAGON_F2_sfmax", -1, 0, 0, -1},
- { "HEXAGON_F2_sfmin", -1, 0, 0, -1},
- { "HEXAGON_F2_sfmpy", -1, 0, 0, -1},
- { "HEXAGON_F2_sfsub", -1, 0, 0, -1},
- { "HEXAGON_M2_acci", -1, 0, 0, -1},
- { "HEXAGON_M2_accii", -1, 0, 0, -1},
- { "HEXAGON_M2_cmaci_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_cmacr_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_cmacs_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_cmacs_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_cmacsc_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_cmacsc_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_cmpyi_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_cmpyr_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_cmpyrs_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_cmpyrs_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_cmpyrsc_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_cmpyrsc_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_cmpys_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_cmpys_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_cmpysc_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_cmpysc_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_cnacs_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_cnacs_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_cnacsc_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_cnacsc_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_dpmpyss_acc_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_dpmpyss_nac_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_dpmpyss_rnd_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_dpmpyss_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_dpmpyuu_acc_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_dpmpyuu_nac_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_dpmpyuu_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_hmmpyh_rs1", -1, 0, 0, -1},
- { "HEXAGON_M2_hmmpyl_rs1", -1, 0, 0, -1},
- { "HEXAGON_M2_maci", -1, 0, 0, -1},
- { "HEXAGON_M2_macsin", -1, 0, 0, -1},
- { "HEXAGON_M2_macsip", -1, 0, 0, -1},
- { "HEXAGON_M2_mmachs_rs0", -1, 0, 0, -1},
- { "HEXAGON_M2_mmachs_rs1", -1, 0, 0, -1},
- { "HEXAGON_M2_mmachs_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mmachs_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mmacls_rs0", -1, 0, 0, -1},
- { "HEXAGON_M2_mmacls_rs1", -1, 0, 0, -1},
- { "HEXAGON_M2_mmacls_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mmacls_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mmacuhs_rs0", -1, 0, 0, -1},
- { "HEXAGON_M2_mmacuhs_rs1", -1, 0, 0, -1},
- { "HEXAGON_M2_mmacuhs_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mmacuhs_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mmaculs_rs0", -1, 0, 0, -1},
- { "HEXAGON_M2_mmaculs_rs1", -1, 0, 0, -1},
- { "HEXAGON_M2_mmaculs_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mmaculs_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mmpyh_rs0", -1, 0, 0, -1},
- { "HEXAGON_M2_mmpyh_rs1", -1, 0, 0, -1},
- { "HEXAGON_M2_mmpyh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mmpyh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mmpyl_rs0", -1, 0, 0, -1},
- { "HEXAGON_M2_mmpyl_rs1", -1, 0, 0, -1},
- { "HEXAGON_M2_mmpyl_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mmpyl_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mmpyuh_rs0", -1, 0, 0, -1},
- { "HEXAGON_M2_mmpyuh_rs1", -1, 0, 0, -1},
- { "HEXAGON_M2_mmpyuh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mmpyuh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mmpyul_rs0", -1, 0, 0, -1},
- { "HEXAGON_M2_mmpyul_rs1", -1, 0, 0, -1},
- { "HEXAGON_M2_mmpyul_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mmpyul_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_acc_hh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_acc_hh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_acc_hl_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_acc_hl_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_acc_lh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_acc_lh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_acc_ll_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_acc_ll_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_acc_sat_hh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_acc_sat_hh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_acc_sat_hl_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_acc_sat_hl_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_acc_sat_lh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_acc_sat_lh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_acc_sat_ll_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_acc_sat_ll_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_hh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_hh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_hl_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_hl_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_lh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_lh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_ll_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_ll_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_nac_hh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_nac_hh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_nac_hl_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_nac_hl_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_nac_lh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_nac_lh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_nac_ll_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_nac_ll_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_nac_sat_hh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_nac_sat_hh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_nac_sat_hl_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_nac_sat_hl_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_nac_sat_lh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_nac_sat_lh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_nac_sat_ll_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_nac_sat_ll_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_rnd_hh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_rnd_hh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_rnd_hl_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_rnd_hl_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_rnd_lh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_rnd_lh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_rnd_ll_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_rnd_ll_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_sat_hh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_sat_hh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_sat_hl_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_sat_hl_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_sat_lh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_sat_lh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_sat_ll_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_sat_ll_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_sat_rnd_hh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_sat_rnd_hh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_sat_rnd_hl_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_sat_rnd_hl_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_sat_rnd_lh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_sat_rnd_lh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_sat_rnd_ll_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_sat_rnd_ll_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpy_up", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_acc_hh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_acc_hh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_acc_hl_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_acc_hl_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_acc_lh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_acc_lh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_acc_ll_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_acc_ll_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_hh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_hh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_hl_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_hl_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_lh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_lh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_ll_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_ll_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_nac_hh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_nac_hh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_nac_hl_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_nac_hl_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_nac_lh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_nac_lh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_nac_ll_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_nac_ll_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_rnd_hh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_rnd_hh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_rnd_hl_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_rnd_hl_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_rnd_lh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_rnd_lh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_rnd_ll_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyd_rnd_ll_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyi", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_acc_hh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_acc_hh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_acc_hl_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_acc_hl_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_acc_lh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_acc_lh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_acc_ll_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_acc_ll_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_hh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_hh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_hl_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_hl_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_lh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_lh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_ll_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_ll_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_nac_hh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_nac_hh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_nac_hl_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_nac_hl_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_nac_lh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_nac_lh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_nac_ll_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_nac_ll_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyu_up", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_acc_hh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_acc_hh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_acc_hl_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_acc_hl_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_acc_lh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_acc_lh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_acc_ll_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_acc_ll_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_hh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_hh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_hl_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_hl_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_lh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_lh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_ll_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_ll_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_nac_hh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_nac_hh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_nac_hl_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_nac_hl_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_nac_lh_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_nac_lh_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_nac_ll_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyud_nac_ll_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_mpyui", -1, 0, 0, -1},
- { "HEXAGON_M2_nacci", -1, 0, 0, -1},
- { "HEXAGON_M2_naccii", -1, 0, 0, -1},
- { "HEXAGON_M2_subacc", -1, 0, 0, -1},
- { "HEXAGON_M2_vabsdiffh", -1, 0, 0, -1},
- { "HEXAGON_M2_vabsdiffw", -1, 0, 0, -1},
- { "HEXAGON_M2_vcmac_s0_sat_i", -1, 0, 0, -1},
- { "HEXAGON_M2_vcmac_s0_sat_r", -1, 0, 0, -1},
- { "HEXAGON_M2_vcmpy_s0_sat_i", -1, 0, 0, -1},
- { "HEXAGON_M2_vcmpy_s0_sat_r", -1, 0, 0, -1},
- { "HEXAGON_M2_vcmpy_s1_sat_i", -1, 0, 0, -1},
- { "HEXAGON_M2_vcmpy_s1_sat_r", -1, 0, 0, -1},
- { "HEXAGON_M2_vdmacs_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_vdmacs_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_vdmpyrs_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_vdmpyrs_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_vdmpys_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_vdmpys_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_vmac2", -1, 0, 0, -1},
- { "HEXAGON_M2_vmac2es", -1, 0, 0, -1},
- { "HEXAGON_M2_vmac2es_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_vmac2es_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_vmac2s_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_vmac2s_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_vmpy2es_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_vmpy2es_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_vmpy2s_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_vmpy2s_s0pack", -1, 0, 0, -1},
- { "HEXAGON_M2_vmpy2s_s1", -1, 0, 0, -1},
- { "HEXAGON_M2_vmpy2s_s1pack", -1, 0, 0, -1},
- { "HEXAGON_M2_vrcmaci_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_vrcmaci_s0c", -1, 0, 0, -1},
- { "HEXAGON_M2_vrcmacr_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_vrcmacr_s0c", -1, 0, 0, -1},
- { "HEXAGON_M2_vrcmpyi_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_vrcmpyi_s0c", -1, 0, 0, -1},
- { "HEXAGON_M2_vrcmpyr_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_vrcmpyr_s0c", -1, 0, 0, -1},
- { "HEXAGON_M2_vrmac_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_vrmpy_s0", -1, 0, 0, -1},
- { "HEXAGON_M2_xor_xacc", -1, 0, 0, -1},
- { "HEXAGON_M4_and_and", -1, 0, 0, -1},
- { "HEXAGON_M4_and_andn", -1, 0, 0, -1},
- { "HEXAGON_M4_and_or", -1, 0, 0, -1},
- { "HEXAGON_M4_and_xor", -1, 0, 0, -1},
- { "HEXAGON_M4_or_and", -1, 0, 0, -1},
- { "HEXAGON_M4_or_andn", -1, 0, 0, -1},
- { "HEXAGON_M4_or_or", -1, 0, 0, -1},
- { "HEXAGON_M4_or_xor", -1, 0, 0, -1},
- { "HEXAGON_M4_xor_and", -1, 0, 0, -1},
- { "HEXAGON_M4_xor_andn", -1, 0, 0, -1},
- { "HEXAGON_M4_xor_or", -1, 0, 0, -1},
- { "HEXAGON_M5_vdmacbsu", -1, 0, 0, -1},
- { "HEXAGON_M5_vdmpybsu", -1, 0, 0, -1},
- { "HEXAGON_M5_vmacbsu", -1, 0, 0, -1},
- { "HEXAGON_M5_vmacbuu", -1, 0, 0, -1},
- { "HEXAGON_M5_vmpybsu", -1, 0, 0, -1},
- { "HEXAGON_M5_vmpybuu", -1, 0, 0, -1},
- { "HEXAGON_M5_vrmacbsu", -1, 0, 0, -1},
- { "HEXAGON_M5_vrmacbuu", -1, 0, 0, -1},
- { "HEXAGON_M5_vrmpybsu", -1, 0, 0, -1},
- { "HEXAGON_M5_vrmpybuu", -1, 0, 0, -1},
- { "HEXAGON_S2_addasl_rrri", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_i_p", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_i_p_acc", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_i_p_and", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_i_p_nac", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_i_p_or", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_i_p_xacc", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_i_r", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_i_r_acc", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_i_r_and", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_i_r_nac", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_i_r_or", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_i_r_sat", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_i_r_xacc", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_i_vh", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_i_vw", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_r_p", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_r_p_acc", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_r_p_and", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_r_p_nac", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_r_p_or", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_r_r", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_r_r_acc", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_r_r_and", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_r_r_nac", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_r_r_or", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_r_r_sat", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_r_vh", -1, 0, 0, -1},
- { "HEXAGON_S2_asl_r_vw", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_i_p", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_i_p_acc", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_i_p_and", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_i_p_nac", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_i_p_or", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_i_p_rnd", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_i_p_rnd_goodsyntax", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_i_r", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_i_r_acc", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_i_r_and", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_i_r_nac", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_i_r_or", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_i_r_rnd", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_i_r_rnd_goodsyntax", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_i_svw_trun", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_i_vh", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_i_vw", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_r_p", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_r_p_acc", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_r_p_and", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_r_p_nac", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_r_p_or", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_r_r", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_r_r_acc", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_r_r_and", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_r_r_nac", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_r_r_or", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_r_r_sat", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_r_svw_trun", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_r_vh", -1, 0, 0, -1},
- { "HEXAGON_S2_asr_r_vw", -1, 0, 0, -1},
- { "HEXAGON_S2_cl0", -1, 0, 0, -1},
- { "HEXAGON_S2_cl0p", -1, 0, 0, -1},
- { "HEXAGON_S2_cl1", -1, 0, 0, -1},
- { "HEXAGON_S2_cl1p", -1, 0, 0, -1},
- { "HEXAGON_S2_clb", -1, 0, 0, -1},
- { "HEXAGON_S2_clbnorm", -1, 0, 0, -1},
- { "HEXAGON_S2_clbp", -1, 0, 0, -1},
- { "HEXAGON_S2_clrbit_i", -1, 0, 0, -1},
- { "HEXAGON_S2_clrbit_r", -1, 0, 0, -1},
- { "HEXAGON_S2_ct0", -1, 0, 0, -1},
- { "HEXAGON_S2_ct1", -1, 0, 0, -1},
- { "HEXAGON_S2_extractu", -1, 0, 0, -1},
- { "HEXAGON_S2_extractu_rp", -1, 0, 0, -1},
- { "HEXAGON_S2_extractup", -1, 0, 0, -1},
- { "HEXAGON_S2_extractup_rp", -1, 0, 0, -1},
- { "HEXAGON_S2_lsl_r_p", -1, 0, 0, -1},
- { "HEXAGON_S2_lsl_r_p_acc", -1, 0, 0, -1},
- { "HEXAGON_S2_lsl_r_p_and", -1, 0, 0, -1},
- { "HEXAGON_S2_lsl_r_p_nac", -1, 0, 0, -1},
- { "HEXAGON_S2_lsl_r_p_or", -1, 0, 0, -1},
- { "HEXAGON_S2_lsl_r_r", -1, 0, 0, -1},
- { "HEXAGON_S2_lsl_r_r_acc", -1, 0, 0, -1},
- { "HEXAGON_S2_lsl_r_r_and", -1, 0, 0, -1},
- { "HEXAGON_S2_lsl_r_r_nac", -1, 0, 0, -1},
- { "HEXAGON_S2_lsl_r_r_or", -1, 0, 0, -1},
- { "HEXAGON_S2_lsl_r_vh", -1, 0, 0, -1},
- { "HEXAGON_S2_lsl_r_vw", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_i_p", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_i_p_acc", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_i_p_and", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_i_p_nac", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_i_p_or", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_i_p_xacc", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_i_r", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_i_r_acc", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_i_r_and", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_i_r_nac", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_i_r_or", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_i_r_xacc", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_i_vh", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_i_vw", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_r_p", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_r_p_acc", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_r_p_and", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_r_p_nac", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_r_p_or", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_r_r", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_r_r_acc", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_r_r_and", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_r_r_nac", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_r_r_or", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_r_vh", -1, 0, 0, -1},
- { "HEXAGON_S2_lsr_r_vw", -1, 0, 0, -1},
- { "HEXAGON_S2_packhl", -1, 0, 0, -1},
- { "HEXAGON_S2_parityp", -1, 0, 0, -1},
- { "HEXAGON_S2_setbit_i", -1, 0, 0, -1},
- { "HEXAGON_S2_setbit_r", -1, 0, 0, -1},
- { "HEXAGON_S2_shuffeb", -1, 0, 0, -1},
- { "HEXAGON_S2_shuffeh", -1, 0, 0, -1},
- { "HEXAGON_S2_shuffob", -1, 0, 0, -1},
- { "HEXAGON_S2_shuffoh", -1, 0, 0, -1},
- { "HEXAGON_S2_svsathb", -1, 0, 0, -1},
- { "HEXAGON_S2_svsathub", -1, 0, 0, -1},
- { "HEXAGON_S2_togglebit_i", -1, 0, 0, -1},
- { "HEXAGON_S2_togglebit_r", -1, 0, 0, -1},
- { "HEXAGON_S2_tstbit_i", -1, 0, 0, -1},
- { "HEXAGON_S2_tstbit_r", -1, 0, 0, -1},
- { "HEXAGON_S2_valignib", -1, 0, 0, -1},
- { "HEXAGON_S2_valignrb", -1, 0, 0, -1},
- { "HEXAGON_S2_vcrotate", -1, 0, 0, -1},
- { "HEXAGON_S2_vrndpackwh", -1, 0, 0, -1},
- { "HEXAGON_S2_vrndpackwhs", -1, 0, 0, -1},
- { "HEXAGON_S2_vsathb", -1, 0, 0, -1},
- { "HEXAGON_S2_vsathb_nopack", -1, 0, 0, -1},
- { "HEXAGON_S2_vsathub", -1, 0, 0, -1},
- { "HEXAGON_S2_vsathub_nopack", -1, 0, 0, -1},
- { "HEXAGON_S2_vsatwh", -1, 0, 0, -1},
- { "HEXAGON_S2_vsatwh_nopack", -1, 0, 0, -1},
- { "HEXAGON_S2_vsatwuh", -1, 0, 0, -1},
- { "HEXAGON_S2_vsatwuh_nopack", -1, 0, 0, -1},
- { "HEXAGON_S2_vsplatrb", -1, 0, 0, -1},
- { "HEXAGON_S2_vsplatrh", -1, 0, 0, -1},
- { "HEXAGON_S2_vsxtbh", -1, 0, 0, -1},
- { "HEXAGON_S2_vsxthw", -1, 0, 0, -1},
- { "HEXAGON_S2_vtrunehb", -1, 0, 0, -1},
- { "HEXAGON_S2_vtrunewh", -1, 0, 0, -1},
- { "HEXAGON_S2_vtrunohb", -1, 0, 0, -1},
- { "HEXAGON_S2_vtrunowh", -1, 0, 0, -1},
- { "HEXAGON_S2_vzxtbh", -1, 0, 0, -1},
- { "HEXAGON_S2_vzxthw", -1, 0, 0, -1},
- { "HEXAGON_S4_or_andi", -1, 0, 0, -1},
- { "HEXAGON_S4_or_andix", -1, 0, 0, -1},
- { "HEXAGON_S4_or_ori", -1, 0, 0, -1},
- { "HEXAGON_S5_asrhub_rnd_sat_goodsyntax", -1, 0, 0, -1},
- { "HEXAGON_S5_asrhub_sat", -1, 0, 0, -1},
- { "HEXAGON_S5_popcountp", -1, 0, 0, -1},
- { "HEXAGON_S5_vasrhrnd_goodsyntax", -1, 0, 0, -1},
- { "HEXAGON_circ_ldd", -1, 0, 0, -1},
- { "HI", -1, 0, 0, -1},
- { "HI_jt", -1, 0, 0, -1},
- { "HI_label", -1, 0, 0, -1},
- { "HIi", -1, 0, 0, -1},
- { "Hexagon_A2_addpsat", -1, 0, 0, -1},
- { "Hexagon_A2_addsp", -1, 0, 0, -1},
- { "Hexagon_A2_maxp", -1, 0, 0, -1},
- { "Hexagon_A2_maxup", -1, 0, 0, -1},
- { "Hexagon_A4_andn", -1, 0, 0, -1},
- { "Hexagon_A4_combineir", -1, 0, 0, -1},
- { "Hexagon_A4_combineri", -1, 0, 0, -1},
- { "Hexagon_A4_orn", -1, 0, 0, -1},
- { "Hexagon_A4_rcmpeq", -1, 0, 0, -1},
- { "Hexagon_A4_rcmpeqi", -1, 0, 0, -1},
- { "Hexagon_A4_rcmpneq", -1, 0, 0, -1},
- { "Hexagon_A4_rcmpneqi", -1, 0, 0, -1},
- { "Hexagon_C2_bitsclr", -1, 0, 0, -1},
- { "Hexagon_C2_bitsclri", -1, 0, 0, -1},
- { "Hexagon_C2_bitsset", -1, 0, 0, -1},
- { "Hexagon_C4_and_and", -1, 0, 0, -1},
- { "Hexagon_C4_and_andn", -1, 0, 0, -1},
- { "Hexagon_C4_and_or", -1, 0, 0, -1},
- { "Hexagon_C4_and_orn", -1, 0, 0, -1},
- { "Hexagon_C4_cmplte", -1, 0, 0, -1},
- { "Hexagon_C4_cmpltei", -1, 0, 0, -1},
- { "Hexagon_C4_cmplteu", -1, 0, 0, -1},
- { "Hexagon_C4_cmplteui", -1, 0, 0, -1},
- { "Hexagon_C4_cmpneq", -1, 0, 0, -1},
- { "Hexagon_C4_cmpneqi", -1, 0, 0, -1},
- { "Hexagon_C4_fastcorner9", -1, 0, 0, -1},
- { "Hexagon_C4_fastcorner9_not", -1, 0, 0, -1},
- { "Hexagon_C4_or_and", -1, 0, 0, -1},
- { "Hexagon_C4_or_andn", -1, 0, 0, -1},
- { "Hexagon_C4_or_or", -1, 0, 0, -1},
- { "Hexagon_C4_or_orn", -1, 0, 0, -1},
- { "Hexagon_M2_mpysmi", -1, 0, 0, -1},
- { "Hexagon_M2_vradduh", -1, 0, 0, -1},
- { "Hexagon_M2_vrcmpys_acc_s1", -1, 0, 0, -1},
- { "Hexagon_M2_vrcmpys_s1", -1, 0, 0, -1},
- { "Hexagon_M2_vrcmpys_s1rp", -1, 0, 0, -1},
- { "Hexagon_M4_xor_xacc", -1, 0, 0, -1},
- { "Hexagon_S2_brev", -1, 0, 0, -1},
- { "Hexagon_S2_deinterleave", -1, 0, 0, -1},
- { "Hexagon_S2_insert", -1, 0, 0, -1},
- { "Hexagon_S2_insert_rp", -1, 0, 0, -1},
- { "Hexagon_S2_insertp", -1, 0, 0, -1},
- { "Hexagon_S2_insertp_rp", -1, 0, 0, -1},
- { "Hexagon_S2_interleave", -1, 0, 0, -1},
- { "Hexagon_S2_lfsp", -1, 0, 0, -1},
- { "Hexagon_S2_tableidxb_goodsyntax", -1, 0, 0, -1},
- { "Hexagon_S2_tableidxd_goodsyntax", -1, 0, 0, -1},
- { "Hexagon_S2_tableidxh_goodsyntax", -1, 0, 0, -1},
- { "Hexagon_S2_tableidxw_goodsyntax", -1, 0, 0, -1},
- { "Hexagon_S2_vspliceib", -1, 0, 0, -1},
- { "Hexagon_S2_vsplicerb", -1, 0, 0, -1},
- { "Hexagon_S4_addaddi", -1, 0, 0, -1},
- { "Hexagon_S4_andnp", -1, 0, 0, -1},
- { "Hexagon_S4_ornp", -1, 0, 0, -1},
- { "Hexagon_S4_subaddi", -1, 0, 0, -1},
- { "IMMEXT", -1, 0, 0, -1},
- { "JMP", -1, 0, 0, -1},
- { "JMPR", -1, 0, 0, -1},
- { "JMPR_cNotPt", -1, 0, 0, -1},
- { "JMPR_cPt", -1, 0, 0, -1},
- { "JMPR_cdnNotPnt", -1, 0, 0, -1},
- { "JMPR_cdnNotPt_V3", -1, 0, 0, -1},
- { "JMPR_cdnPnt", -1, 0, 0, -1},
- { "JMPR_cdnPt_V3", -1, 0, 0, -1},
- { "JMP_EQriNotPnt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_EQriNotPnt_nv_V4", -1, 0, 0, -1},
- { "JMP_EQriNotPntneg_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_EQriNotPntneg_nv_V4", -1, 0, 0, -1},
- { "JMP_EQriNotPt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_EQriNotPt_nv_V4", -1, 0, 0, -1},
- { "JMP_EQriNotPtneg_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_EQriNotPtneg_nv_V4", -1, 0, 0, -1},
- { "JMP_EQriPnt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_EQriPnt_nv_V4", -1, 0, 0, -1},
- { "JMP_EQriPntneg_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_EQriPntneg_nv_V4", -1, 0, 0, -1},
- { "JMP_EQriPt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_EQriPt_nv_V4", -1, 0, 0, -1},
- { "JMP_EQriPtneg_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_EQriPtneg_nv_V4", -1, 0, 0, -1},
- { "JMP_EQrrNotPnt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_EQrrNotPnt_nv_V4", -1, 0, 0, -1},
- { "JMP_EQrrNotPt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_EQrrNotPt_nv_V4", -1, 0, 0, -1},
- { "JMP_EQrrPnt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_EQrrPnt_nv_V4", -1, 0, 0, -1},
- { "JMP_EQrrPt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_EQrrPt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUriNotPnt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUriNotPnt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUriNotPt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUriNotPt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUriPnt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUriPnt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUriPt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUriPt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUrrNotPnt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUrrNotPnt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUrrNotPt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUrrNotPt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUrrPnt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUrrPnt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUrrPt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUrrPt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUrrdnNotPnt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUrrdnNotPnt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUrrdnNotPt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUrrdnNotPt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUrrdnPnt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUrrdnPnt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUrrdnPt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTUrrdnPt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTriNotPnt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTriNotPnt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTriNotPntneg_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTriNotPntneg_nv_V4", -1, 0, 0, -1},
- { "JMP_GTriNotPt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTriNotPt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTriNotPtneg_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTriNotPtneg_nv_V4", -1, 0, 0, -1},
- { "JMP_GTriPnt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTriPnt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTriPntneg_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTriPntneg_nv_V4", -1, 0, 0, -1},
- { "JMP_GTriPt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTriPt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTriPtneg_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTriPtneg_nv_V4", -1, 0, 0, -1},
- { "JMP_GTrrNotPnt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTrrNotPnt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTrrNotPt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTrrNotPt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTrrPnt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTrrPnt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTrrPt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTrrPt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTrrdnNotPnt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTrrdnNotPnt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTrrdnNotPt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTrrdnNotPt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTrrdnPnt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTrrdnPnt_nv_V4", -1, 0, 0, -1},
- { "JMP_GTrrdnPt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_GTrrdnPt_nv_V4", -1, 0, 0, -1},
- { "JMP_TSTBITr0NotPnt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_TSTBITr0NotPnt_nv_V4", -1, 0, 0, -1},
- { "JMP_TSTBITr0NotPt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_TSTBITr0NotPt_nv_V4", -1, 0, 0, -1},
- { "JMP_TSTBITr0Pnt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_TSTBITr0Pnt_nv_V4", -1, 0, 0, -1},
- { "JMP_TSTBITr0Pt_ie_nv_V4", -1, 0, 0, -1},
- { "JMP_TSTBITr0Pt_nv_V4", -1, 0, 0, -1},
- { "JMP_c", -1, 0, 0, -1},
- { "JMP_cNot", -1, 0, 0, -1},
- { "JMP_cdnNotPnt", -1, 0, 0, -1},
- { "JMP_cdnNotPt", -1, 0, 0, -1},
- { "JMP_cdnPnt", -1, 0, 0, -1},
- { "JMP_cdnPt", -1, 0, 0, -1},
- { "LDb_GP", -1, 0, 0, -1},
- { "LDb_GP_V4", -1, 0, 0, -1},
- { "LDb_GP_cNotPt_V4", -1, 0, 0, -1},
- { "LDb_GP_cPt_V4", -1, 0, 0, -1},
- { "LDb_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDb_GP_cdnPt_V4", -1, 0, 0, -1},
- { "LDd_GP", -1, 0, 0, -1},
- { "LDd_GP_V4", -1, 0, 0, -1},
- { "LDd_GP_cNotPt_V4", -1, 0, 0, -1},
- { "LDd_GP_cPt_V4", -1, 0, 0, -1},
- { "LDd_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDd_GP_cdnPt_V4", -1, 0, 0, -1},
- { "LDh_GP", -1, 0, 0, -1},
- { "LDh_GP_V4", -1, 0, 0, -1},
- { "LDh_GP_cNotPt_V4", -1, 0, 0, -1},
- { "LDh_GP_cPt_V4", -1, 0, 0, -1},
- { "LDh_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDh_GP_cdnPt_V4", -1, 0, 0, -1},
- { "LDrib", 2, -1024, 1023, Hexagon::LDrib_indexed_shl_V4},
- { "LDrib_GP", -1, 0, 0, -1},
- { "LDrib_GP_V4", -1, 0, 0, -1},
- { "LDrib_GP_cNotPt_V4", -1, 0, 0, -1},
- { "LDrib_GP_cPt_V4", -1, 0, 0, -1},
- { "LDrib_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDrib_GP_cdnPt_V4", -1, 0, 0, -1},
- { "LDrib_abs_V4", 1, 0, 0, Hexagon::LDrib_indexed},
- { "LDrib_abs_cNotPt_V4", 2, 0, 0, Hexagon::LDrib_indexed_cNotPt},
- { "LDrib_abs_cPt_V4", 2, 0, 0, Hexagon::LDrib_indexed_cPt},
- { "LDrib_abs_cdnNotPt_V4", 2, 0, 0, Hexagon::LDrib_indexed_cdnNotPt},
- { "LDrib_abs_cdnPt_V4", 2, 0, 0, Hexagon::LDrib_indexed_cdnPt},
- { "LDrib_abs_set_V4", 2, 0, 0, -1},
- { "LDrib_abs_setimm_V4", 2, 0, 63, -1},
- { "LDrib_cNotPt", 3, -1024, 1023, Hexagon::LDrib_indexed_shl_cNotPt_V4},
- { "LDrib_cPt", 3, -1024, 1023, Hexagon::LDrib_indexed_shl_cPt_V4},
- { "LDrib_cdnNotPt", 3, -1024, 1023, Hexagon::LDrib_indexed_shl_cdnNotPt_V4},
- { "LDrib_cdnPt", 3, -1024, 1023, Hexagon::LDrib_indexed_shl_cdnPt_V4},
- { "LDrib_imm_abs_V4", 1, 0, 63, Hexagon::LDrib_indexed},
- { "LDrib_imm_abs_cNotPt_V4", 2, 0, 63, Hexagon::LDrib_indexed_cNotPt},
- { "LDrib_imm_abs_cPt_V4", 2, 0, 63, Hexagon::LDrib_indexed_cPt},
- { "LDrib_imm_abs_cdnNotPt_V4", 2, 0, 63, Hexagon::LDrib_indexed_cdnNotPt},
- { "LDrib_imm_abs_cdnPt_V4", 2, 0, 63, Hexagon::LDrib_indexed_cdnPt},
- { "LDrib_ind_lo_V4", 3, 0, 0, -1},
- { "LDrib_indexed", 2, -1024, 1023, Hexagon::LDrib_indexed_shl_V4},
- { "LDrib_indexed_V4", -1, 0, 0, -1},
- { "LDrib_indexed_cNotPt", 3, 0, 63, Hexagon::LDrib_indexed_shl_cNotPt_V4},
- { "LDrib_indexed_cNotPt_V4", -1, 0, 0, -1},
- { "LDrib_indexed_cPt", 3, 0, 63, Hexagon::LDrib_indexed_shl_cPt_V4},
- { "LDrib_indexed_cPt_V4", -1, 0, 0, -1},
- { "LDrib_indexed_cdnNotPt", 3, 0, 63, Hexagon::LDrib_indexed_shl_cdnNotPt_V4},
- { "LDrib_indexed_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDrib_indexed_cdnPt", 3, 0, 63, Hexagon::LDrib_indexed_shl_cdnPt_V4},
- { "LDrib_indexed_cdnPt_V4", -1, 0, 0, -1},
- { "LDrib_indexed_shl_V4", -1, 0, 0, -1},
- { "LDrib_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
- { "LDrib_indexed_shl_cPt_V4", -1, 0, 0, -1},
- { "LDrib_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDrib_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
- { "LDrid", 2, -8192, 8184, Hexagon::LDrid_indexed_shl_V4},
- { "LDrid_GP", -1, 0, 0, -1},
- { "LDrid_GP_V4", -1, 0, 0, -1},
- { "LDrid_GP_cNotPt_V4", -1, 0, 0, -1},
- { "LDrid_GP_cPt_V4", -1, 0, 0, -1},
- { "LDrid_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDrid_GP_cdnPt_V4", -1, 0, 0, -1},
- { "LDrid_abs_V4", 1, 0, 0, Hexagon::LDrid_indexed},
- { "LDrid_abs_cNotPt_V4", 2, 0, 0, Hexagon::LDrid_indexed_cNotPt},
- { "LDrid_abs_cPt_V4", 2, 0, 0, Hexagon::LDrid_indexed_cPt},
- { "LDrid_abs_cdnNotPt_V4", 2, 0, 0, Hexagon::LDrid_indexed_cdnNotPt},
- { "LDrid_abs_cdnPt_V4", 2, 0, 0, Hexagon::LDrid_indexed_cdnPt},
- { "LDrid_abs_set_V4", 2, 0, 0, -1},
- { "LDrid_abs_setimm_V4", 2, 0, 63, -1},
- { "LDrid_cNotPt", 3, -8192, 8184, Hexagon::LDrid_indexed_shl_cNotPt_V4},
- { "LDrid_cPt", 3, -8192, 8184, Hexagon::LDrid_indexed_shl_cPt_V4},
- { "LDrid_cdnNotPt", 3, -8192, 8184, Hexagon::LDrid_indexed_shl_cdnNotPt_V4},
- { "LDrid_cdnPt", 3, -8192, 8184, Hexagon::LDrid_indexed_shl_cdnPt_V4},
- { "LDrid_f", 2, -8192, 8184, Hexagon::LDrid_indexed_shl_V4},
- { "LDrid_ind_lo_V4", 3, 0, 0, -1},
- { "LDrid_indexed", 2, -8192, 8184, Hexagon::LDrid_indexed_shl_V4},
- { "LDrid_indexed_V4", -1, 0, 0, -1},
- { "LDrid_indexed_cNotPt", 3, 0, 504, Hexagon::LDrid_indexed_shl_cNotPt_V4},
- { "LDrid_indexed_cNotPt_V4", -1, 0, 0, -1},
- { "LDrid_indexed_cPt", 3, 0, 504, Hexagon::LDrid_indexed_shl_cPt_V4},
- { "LDrid_indexed_cPt_V4", -1, 0, 0, -1},
- { "LDrid_indexed_cdnNotPt", 3, 0, 504, Hexagon::LDrid_indexed_shl_cdnNotPt_V4},
- { "LDrid_indexed_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDrid_indexed_cdnPt", 3, 0, 504, Hexagon::LDrid_indexed_shl_cdnPt_V4},
- { "LDrid_indexed_cdnPt_V4", -1, 0, 0, -1},
- { "LDrid_indexed_f", 2, -8192, 8184, Hexagon::LDrid_indexed_shl_V4},
- { "LDrid_indexed_shl_V4", -1, 0, 0, -1},
- { "LDrid_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
- { "LDrid_indexed_shl_cPt_V4", -1, 0, 0, -1},
- { "LDrid_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDrid_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
- { "LDrih", 2, -2048, 2046, Hexagon::LDrih_indexed_shl_V4},
- { "LDrih_GP", -1, 0, 0, -1},
- { "LDrih_GP_V4", -1, 0, 0, -1},
- { "LDrih_GP_cNotPt_V4", -1, 0, 0, -1},
- { "LDrih_GP_cPt_V4", -1, 0, 0, -1},
- { "LDrih_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDrih_GP_cdnPt_V4", -1, 0, 0, -1},
- { "LDrih_abs_V4", 1, 0, 0, Hexagon::LDrih_indexed},
- { "LDrih_abs_cNotPt_V4", 2, 0, 0, Hexagon::LDrih_indexed_cNotPt},
- { "LDrih_abs_cPt_V4", 2, 0, 0, Hexagon::LDrih_indexed_cPt},
- { "LDrih_abs_cdnNotPt_V4", 2, 0, 0, Hexagon::LDrih_indexed_cdnNotPt},
- { "LDrih_abs_cdnPt_V4", 2, 0, 0, Hexagon::LDrih_indexed_cdnPt},
- { "LDrih_abs_set_V4", 2, 0, 0, -1},
- { "LDrih_abs_setimm_V4", 2, 0, 63, -1},
- { "LDrih_cNotPt", 3, -2048, 2046, Hexagon::LDrih_indexed_shl_cNotPt_V4},
- { "LDrih_cPt", 3, -2048, 2046, Hexagon::LDrih_indexed_shl_cPt_V4},
- { "LDrih_cdnNotPt", 3, -2048, 2046, Hexagon::LDrih_indexed_shl_cdnNotPt_V4},
- { "LDrih_cdnPt", 3, -2048, 2046, Hexagon::LDrih_indexed_shl_cdnPt_V4},
- { "LDrih_imm_abs_V4", 1, 0, 63, Hexagon::LDrih_indexed},
- { "LDrih_imm_abs_cNotPt_V4", 2, 0, 63, Hexagon::LDrih_indexed_cNotPt},
- { "LDrih_imm_abs_cPt_V4", 2, 0, 63, Hexagon::LDrih_indexed_cPt},
- { "LDrih_imm_abs_cdnNotPt_V4", 2, 0, 63, Hexagon::LDrih_indexed_cdnNotPt},
- { "LDrih_imm_abs_cdnPt_V4", 2, 0, 63, Hexagon::LDrih_indexed_cdnPt},
- { "LDrih_ind_lo_V4", 3, 0, 0, -1},
- { "LDrih_indexed", 2, -2048, 2046, Hexagon::LDrih_indexed_shl_V4},
- { "LDrih_indexed_V4", -1, 0, 0, -1},
- { "LDrih_indexed_cNotPt", 3, 0, 126, Hexagon::LDrih_indexed_shl_cNotPt_V4},
- { "LDrih_indexed_cNotPt_V4", -1, 0, 0, -1},
- { "LDrih_indexed_cPt", 3, 0, 126, Hexagon::LDrih_indexed_shl_cPt_V4},
- { "LDrih_indexed_cPt_V4", -1, 0, 0, -1},
- { "LDrih_indexed_cdnNotPt", 3, 0, 126, Hexagon::LDrih_indexed_shl_cdnNotPt_V4},
- { "LDrih_indexed_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDrih_indexed_cdnPt", 3, 0, 126, Hexagon::LDrih_indexed_shl_cdnPt_V4},
- { "LDrih_indexed_cdnPt_V4", -1, 0, 0, -1},
- { "LDrih_indexed_shl_V4", -1, 0, 0, -1},
- { "LDrih_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
- { "LDrih_indexed_shl_cPt_V4", -1, 0, 0, -1},
- { "LDrih_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDrih_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
- { "LDriub", 2, -1024, 1023, Hexagon::LDriub_ae_indexed_shl_V4},
- { "LDriub_GP", -1, 0, 0, -1},
- { "LDriub_GP_V4", -1, 0, 0, -1},
- { "LDriub_GP_cNotPt_V4", -1, 0, 0, -1},
- { "LDriub_GP_cPt_V4", -1, 0, 0, -1},
- { "LDriub_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDriub_GP_cdnPt_V4", -1, 0, 0, -1},
- { "LDriub_abs_V4", 1, 0, 0, Hexagon::LDriub_indexed},
- { "LDriub_abs_cNotPt_V4", 2, 0, 0, Hexagon::LDriub_indexed_cNotPt},
- { "LDriub_abs_cPt_V4", 2, 0, 0, Hexagon::LDriub_indexed_cPt},
- { "LDriub_abs_cdnNotPt_V4", 2, 0, 0, Hexagon::LDriub_indexed_cdnNotPt},
- { "LDriub_abs_cdnPt_V4", 2, 0, 0, Hexagon::LDriub_indexed_cdnPt},
- { "LDriub_abs_set_V4", 2, 0, 0, -1},
- { "LDriub_abs_setimm_V4", 2, 0, 63, -1},
- { "LDriub_ae_indexed_V4", -1, 0, 0, -1},
- { "LDriub_ae_indexed_shl_V4", -1, 0, 0, -1},
- { "LDriub_cNotPt", 3, -1024, 1023, Hexagon::LDriub_indexed_shl_cNotPt_V4},
- { "LDriub_cPt", 3, -1024, 1023, Hexagon::LDriub_indexed_shl_cPt_V4},
- { "LDriub_cdnNotPt", 3, -1024, 1023, Hexagon::LDriub_indexed_shl_cdnNotPt_V4},
- { "LDriub_cdnPt", 3, -1024, 1023, Hexagon::LDriub_indexed_shl_cdnPt_V4},
- { "LDriub_imm_abs_V4", 1, 0, 63, Hexagon::LDriub_indexed},
- { "LDriub_imm_abs_cNotPt_V4", 2, 0, 63, Hexagon::LDriub_indexed_cNotPt},
- { "LDriub_imm_abs_cPt_V4", 2, 0, 63, Hexagon::LDriub_indexed_cPt},
- { "LDriub_imm_abs_cdnNotPt_V4", 2, 0, 63, Hexagon::LDriub_indexed_cdnNotPt},
- { "LDriub_imm_abs_cdnPt_V4", 2, 0, 63, Hexagon::LDriub_indexed_cdnPt},
- { "LDriub_ind_lo_V4", 3, 0, 0, -1},
- { "LDriub_indexed", 2, -1024, 1023, Hexagon::LDriub_ae_indexed_shl_V4},
- { "LDriub_indexed_V4", -1, 0, 0, -1},
- { "LDriub_indexed_cNotPt", 3, 0, 63, Hexagon::LDriub_indexed_shl_cNotPt_V4},
- { "LDriub_indexed_cNotPt_V4", -1, 0, 0, -1},
- { "LDriub_indexed_cPt", 3, 0, 63, Hexagon::LDriub_indexed_shl_cPt_V4},
- { "LDriub_indexed_cPt_V4", -1, 0, 0, -1},
- { "LDriub_indexed_cdnNotPt", 3, 0, 63, Hexagon::LDriub_indexed_shl_cdnNotPt_V4},
- { "LDriub_indexed_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDriub_indexed_cdnPt", 3, 0, 63, Hexagon::LDriub_indexed_shl_cdnPt_V4},
- { "LDriub_indexed_cdnPt_V4", -1, 0, 0, -1},
- { "LDriub_indexed_shl_V4", -1, 0, 0, -1},
- { "LDriub_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
- { "LDriub_indexed_shl_cPt_V4", -1, 0, 0, -1},
- { "LDriub_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDriub_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
- { "LDriuh", 2, -2048, 2046, Hexagon::LDriuh_ae_indexed_shl_V4},
- { "LDriuh_GP", -1, 0, 0, -1},
- { "LDriuh_GP_V4", -1, 0, 0, -1},
- { "LDriuh_GP_cNotPt_V4", -1, 0, 0, -1},
- { "LDriuh_GP_cPt_V4", -1, 0, 0, -1},
- { "LDriuh_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDriuh_GP_cdnPt_V4", -1, 0, 0, -1},
- { "LDriuh_abs_V4", 1, 0, 0, Hexagon::LDriuh_indexed},
- { "LDriuh_abs_cNotPt_V4", 2, 0, 0, Hexagon::LDriuh_indexed_cNotPt},
- { "LDriuh_abs_cPt_V4", 2, 0, 0, Hexagon::LDriuh_indexed_cPt},
- { "LDriuh_abs_cdnNotPt_V4", 2, 0, 0, Hexagon::LDriuh_indexed_cdnNotPt},
- { "LDriuh_abs_cdnPt_V4", 2, 0, 0, Hexagon::LDriuh_indexed_cdnPt},
- { "LDriuh_abs_set_V4", 2, 0, 0, -1},
- { "LDriuh_abs_setimm_V4", 2, 0, 63, -1},
- { "LDriuh_ae_indexed_V4", -1, 0, 0, -1},
- { "LDriuh_ae_indexed_shl_V4", -1, 0, 0, -1},
- { "LDriuh_cNotPt", 3, -2048, 2046, Hexagon::LDriuh_indexed_shl_cNotPt_V4},
- { "LDriuh_cPt", 3, -2048, 2046, Hexagon::LDriuh_indexed_shl_cPt_V4},
- { "LDriuh_cdnNotPt", 3, -2048, 2046, Hexagon::LDriuh_indexed_shl_cdnNotPt_V4},
- { "LDriuh_cdnPt", 3, -2048, 2046, Hexagon::LDriuh_indexed_shl_cdnPt_V4},
- { "LDriuh_imm_abs_V4", 1, 0, 63, Hexagon::LDriuh_indexed},
- { "LDriuh_imm_abs_cNotPt_V4", 2, 0, 63, Hexagon::LDriuh_indexed_cNotPt},
- { "LDriuh_imm_abs_cPt_V4", 2, 0, 63, Hexagon::LDriuh_indexed_cPt},
- { "LDriuh_imm_abs_cdnNotPt_V4", 2, 0, 63, Hexagon::LDriuh_indexed_cdnNotPt},
- { "LDriuh_imm_abs_cdnPt_V4", 2, 0, 63, Hexagon::LDriuh_indexed_cdnPt},
- { "LDriuh_ind_lo_V4", 3, 0, 0, -1},
- { "LDriuh_indexed", 2, -2048, 2046, Hexagon::LDriuh_ae_indexed_shl_V4},
- { "LDriuh_indexed_V4", -1, 0, 0, -1},
- { "LDriuh_indexed_cNotPt", 3, 0, 126, Hexagon::LDriuh_indexed_shl_cNotPt_V4},
- { "LDriuh_indexed_cNotPt_V4", -1, 0, 0, -1},
- { "LDriuh_indexed_cPt", 3, 0, 126, Hexagon::LDriuh_indexed_shl_cPt_V4},
- { "LDriuh_indexed_cPt_V4", -1, 0, 0, -1},
- { "LDriuh_indexed_cdnNotPt", 3, 0, 126, Hexagon::LDriuh_indexed_shl_cdnNotPt_V4},
- { "LDriuh_indexed_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDriuh_indexed_cdnPt", 3, 0, 126, Hexagon::LDriuh_indexed_shl_cdnPt_V4},
- { "LDriuh_indexed_cdnPt_V4", -1, 0, 0, -1},
- { "LDriuh_indexed_shl_V4", -1, 0, 0, -1},
- { "LDriuh_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
- { "LDriuh_indexed_shl_cPt_V4", -1, 0, 0, -1},
- { "LDriuh_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDriuh_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
- { "LDriw", 2, -4096, 4092, Hexagon::LDriw_indexed_shl_V4},
- { "LDriw_GP", -1, 0, 0, -1},
- { "LDriw_GP_V4", -1, 0, 0, -1},
- { "LDriw_GP_cNotPt_V4", -1, 0, 0, -1},
- { "LDriw_GP_cPt_V4", -1, 0, 0, -1},
- { "LDriw_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDriw_GP_cdnPt_V4", -1, 0, 0, -1},
- { "LDriw_abs_V4", 1, 0, 0, Hexagon::LDriw_indexed},
- { "LDriw_abs_cNotPt_V4", 2, 0, 0, Hexagon::LDriw_indexed_cNotPt},
- { "LDriw_abs_cPt_V4", 2, 0, 0, Hexagon::LDriw_indexed_cPt},
- { "LDriw_abs_cdnNotPt_V4", 2, 0, 0, Hexagon::LDriw_indexed_cdnNotPt},
- { "LDriw_abs_cdnPt_V4", 2, 0, 0, Hexagon::LDriw_indexed_cdnPt},
- { "LDriw_abs_set_V4", 2, 0, 0, -1},
- { "LDriw_abs_setimm_V4", 2, 0, 63, -1},
- { "LDriw_cNotPt", 3, -4096, 4092, Hexagon::LDriw_indexed_shl_cNotPt_V4},
- { "LDriw_cPt", 3, -4096, 4092, Hexagon::LDriw_indexed_shl_cPt_V4},
- { "LDriw_cdnNotPt", 3, -4096, 4092, Hexagon::LDriw_indexed_shl_cdnNotPt_V4},
- { "LDriw_cdnPt", 3, -4096, 4092, Hexagon::LDriw_indexed_shl_cdnPt_V4},
- { "LDriw_f", 2, -4096, 4092, Hexagon::LDriw_indexed_shl_V4},
- { "LDriw_imm_abs_V4", 1, 0, 63, Hexagon::LDriw_indexed},
- { "LDriw_imm_abs_cNotPt_V4", 2, 0, 63, Hexagon::LDriw_indexed_cNotPt},
- { "LDriw_imm_abs_cPt_V4", 2, 0, 63, Hexagon::LDriw_indexed_cPt},
- { "LDriw_imm_abs_cdnNotPt_V4", 2, 0, 63, Hexagon::LDriw_indexed_cdnNotPt},
- { "LDriw_imm_abs_cdnPt_V4", 2, 0, 63, Hexagon::LDriw_indexed_cdnPt},
- { "LDriw_ind_lo_V4", 3, 0, 0, -1},
- { "LDriw_indexed", 2, -4096, 4092, Hexagon::LDriw_indexed_shl_V4},
- { "LDriw_indexed_V4", -1, 0, 0, -1},
- { "LDriw_indexed_cNotPt", 3, 0, 252, Hexagon::LDriw_indexed_shl_cNotPt_V4},
- { "LDriw_indexed_cNotPt_V4", -1, 0, 0, -1},
- { "LDriw_indexed_cPt", 3, 0, 252, Hexagon::LDriw_indexed_shl_cPt_V4},
- { "LDriw_indexed_cPt_V4", -1, 0, 0, -1},
- { "LDriw_indexed_cdnNotPt", 3, 0, 252, Hexagon::LDriw_indexed_shl_cdnNotPt_V4},
- { "LDriw_indexed_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDriw_indexed_cdnPt", 3, 0, 252, Hexagon::LDriw_indexed_shl_cdnPt_V4},
- { "LDriw_indexed_cdnPt_V4", -1, 0, 0, -1},
- { "LDriw_indexed_f", 2, -4096, 4092, Hexagon::LDriw_indexed_shl_V4},
- { "LDriw_indexed_shl_V4", -1, 0, 0, -1},
- { "LDriw_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
- { "LDriw_indexed_shl_cPt_V4", -1, 0, 0, -1},
- { "LDriw_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDriw_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
- { "LDriw_pred", 2, -4096, 4092, -1},
- { "LDriw_pred_V4", 2, -4096, 4092, -1},
- { "LDub_GP", -1, 0, 0, -1},
- { "LDub_GP_V4", -1, 0, 0, -1},
- { "LDub_GP_cNotPt_V4", -1, 0, 0, -1},
- { "LDub_GP_cPt_V4", -1, 0, 0, -1},
- { "LDub_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDub_GP_cdnPt_V4", -1, 0, 0, -1},
- { "LDuh_GP", -1, 0, 0, -1},
- { "LDuh_GP_V4", -1, 0, 0, -1},
- { "LDuh_GP_cNotPt_V4", -1, 0, 0, -1},
- { "LDuh_GP_cPt_V4", -1, 0, 0, -1},
- { "LDuh_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDuh_GP_cdnPt_V4", -1, 0, 0, -1},
- { "LDw_GP", -1, 0, 0, -1},
- { "LDw_GP_V4", -1, 0, 0, -1},
- { "LDw_GP_cNotPt_V4", -1, 0, 0, -1},
- { "LDw_GP_cPt_V4", -1, 0, 0, -1},
- { "LDw_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "LDw_GP_cdnPt_V4", -1, 0, 0, -1},
- { "LO", -1, 0, 0, -1},
- { "LOOP0_i", -1, 0, 0, -1},
- { "LOOP0_iext", 0, 0, 0, -1},
- { "LOOP0_r", -1, 0, 0, -1},
- { "LOOP0_rext", 0, 0, 0, -1},
- { "LO_jt", -1, 0, 0, -1},
- { "LO_label", -1, 0, 0, -1},
- { "LOi", -1, 0, 0, -1},
- { "LSL_ADD_rr", -1, 0, 0, -1},
- { "LSL_ADDd_rr", -1, 0, 0, -1},
- { "LSL_AND_rr", -1, 0, 0, -1},
- { "LSL_ANDd_rr", -1, 0, 0, -1},
- { "LSL_OR_rr", -1, 0, 0, -1},
- { "LSL_ORd_rr", -1, 0, 0, -1},
- { "LSL_SUB_rr", -1, 0, 0, -1},
- { "LSL_SUBd_rr", -1, 0, 0, -1},
- { "LSL_rr", -1, 0, 0, -1},
- { "LSLd", -1, 0, 0, -1},
- { "LSLd_rr_xor_V4", -1, 0, 0, -1},
- { "LSLi_V4", -1, 0, 0, -1},
- { "LSR_ADD_ri", -1, 0, 0, -1},
- { "LSR_ADD_rr", -1, 0, 0, -1},
- { "LSR_ADDd_ri", -1, 0, 0, -1},
- { "LSR_ADDd_rr", -1, 0, 0, -1},
- { "LSR_AND_ri", -1, 0, 0, -1},
- { "LSR_AND_rr", -1, 0, 0, -1},
- { "LSR_ANDd_ri", -1, 0, 0, -1},
- { "LSR_ANDd_rr", -1, 0, 0, -1},
- { "LSR_OR_ri", -1, 0, 0, -1},
- { "LSR_OR_rr", -1, 0, 0, -1},
- { "LSR_ORd_ri", -1, 0, 0, -1},
- { "LSR_ORd_rr", -1, 0, 0, -1},
- { "LSR_SUB_ri", -1, 0, 0, -1},
- { "LSR_SUB_rr", -1, 0, 0, -1},
- { "LSR_SUBd_ri", -1, 0, 0, -1},
- { "LSR_SUBd_rr", -1, 0, 0, -1},
- { "LSR_XOR_ri", -1, 0, 0, -1},
- { "LSR_XORd_ri", -1, 0, 0, -1},
- { "LSR_ri", -1, 0, 0, -1},
- { "LSR_rr", -1, 0, 0, -1},
- { "LSRd_ri", -1, 0, 0, -1},
- { "LSRd_rr", -1, 0, 0, -1},
- { "LSRd_rr_xor_V4", -1, 0, 0, -1},
- { "MASK_p", -1, 0, 0, -1},
- { "MAXUd_rr", -1, 0, 0, -1},
- { "MAXUw_rr", -1, 0, 0, -1},
- { "MAXd_rr", -1, 0, 0, -1},
- { "MAXw_dd", -1, 0, 0, -1},
- { "MAXw_rr", -1, 0, 0, -1},
- { "MEMb_ADDSUBi_MEM_V4", -1, 0, 0, -1},
- { "MEMb_ADDSUBi_indexed_MEM_V4", -1, 0, 0, -1},
- { "MEMb_ADDi_MEM_V4", -1, 0, 0, -1},
- { "MEMb_ADDi_indexed_MEM_V4", -1, 0, 0, -1},
- { "MEMb_ADDr_MEM_V4", -1, 0, 0, -1},
- { "MEMb_ADDr_indexed_MEM_V4", -1, 0, 0, -1},
- { "MEMb_ANDr_MEM_V4", -1, 0, 0, -1},
- { "MEMb_ANDr_indexed_MEM_V4", -1, 0, 0, -1},
- { "MEMb_ORr_MEM_V4", -1, 0, 0, -1},
- { "MEMb_ORr_indexed_MEM_V4", -1, 0, 0, -1},
- { "MEMb_SUBi_MEM_V4", -1, 0, 0, -1},
- { "MEMb_SUBi_indexed_MEM_V4", -1, 0, 0, -1},
- { "MEMb_SUBr_MEM_V4", -1, 0, 0, -1},
- { "MEMb_SUBr_indexed_MEM_V4", -1, 0, 0, -1},
- { "MEMh_ADDSUBi_MEM_V4", -1, 0, 0, -1},
- { "MEMh_ADDSUBi_indexed_MEM_V4", -1, 0, 0, -1},
- { "MEMh_ADDi_MEM_V4", -1, 0, 0, -1},
- { "MEMh_ADDi_indexed_MEM_V4", -1, 0, 0, -1},
- { "MEMh_ADDr_MEM_V4", -1, 0, 0, -1},
- { "MEMh_ADDr_indexed_MEM_V4", -1, 0, 0, -1},
- { "MEMh_ANDr_MEM_V4", -1, 0, 0, -1},
- { "MEMh_ANDr_indexed_MEM_V4", -1, 0, 0, -1},
- { "MEMh_ORr_MEM_V4", -1, 0, 0, -1},
- { "MEMh_ORr_indexed_MEM_V4", -1, 0, 0, -1},
- { "MEMh_SUBi_MEM_V4", -1, 0, 0, -1},
- { "MEMh_SUBi_indexed_MEM_V4", -1, 0, 0, -1},
- { "MEMh_SUBr_MEM_V4", -1, 0, 0, -1},
- { "MEMh_SUBr_indexed_MEM_V4", -1, 0, 0, -1},
- { "MEMw_ADDSUBi_MEM_V4", -1, 0, 0, -1},
- { "MEMw_ADDSUBi_indexed_MEM_V4", -1, 0, 0, -1},
- { "MEMw_ADDi_MEM_V4", -1, 0, 0, -1},
- { "MEMw_ADDi_indexed_MEM_V4", 1, 0, 252, -1},
- { "MEMw_ADDr_MEM_V4", -1, 0, 0, -1},
- { "MEMw_ADDr_indexed_MEM_V4", 1, 0, 252, -1},
- { "MEMw_ANDr_MEM_V4", -1, 0, 0, -1},
- { "MEMw_ANDr_indexed_MEM_V4", 1, 0, 252, -1},
- { "MEMw_ORr_MEM_V4", -1, 0, 0, -1},
- { "MEMw_ORr_indexed_MEM_V4", 1, 0, 252, -1},
- { "MEMw_SUBi_MEM_V4", -1, 0, 0, -1},
- { "MEMw_SUBi_indexed_MEM_V4", 1, 0, 252, -1},
- { "MEMw_SUBr_MEM_V4", -1, 0, 0, -1},
- { "MEMw_SUBr_indexed_MEM_V4", 1, 0, 252, -1},
- { "MINUd_rr", -1, 0, 0, -1},
- { "MINUw_rr", -1, 0, 0, -1},
- { "MINd_rr", -1, 0, 0, -1},
- { "MINw_dd", -1, 0, 0, -1},
- { "MINw_rr", -1, 0, 0, -1},
- { "MPY", -1, 0, 0, -1},
- { "MPY64", -1, 0, 0, -1},
- { "MPY64_acc", -1, 0, 0, -1},
- { "MPY64_sub", -1, 0, 0, -1},
- { "MPYI", -1, 0, 0, -1},
- { "MPYI_acc_ri", 3, 0, 255, Hexagon::MPYI_acc_rr},
- { "MPYI_acc_rr", -1, 0, 0, -1},
- { "MPYI_ri", 2, -256, 255, Hexagon::MPYI},
- { "MPYI_rin", -1, 0, 0, -1},
- { "MPYI_riu", 2, 0, 255, -1},
- { "MPYI_sub_ri", 3, 0, 255, -1},
- { "MPYU", -1, 0, 0, -1},
- { "MPYU64", -1, 0, 0, -1},
- { "MPYU64_acc", -1, 0, 0, -1},
- { "MPYU64_sub", -1, 0, 0, -1},
- { "MPY_trsext", -1, 0, 0, -1},
- { "MUX_ii", 2, -128, 127, -1},
- { "MUX_ir", 2, -128, 127, Hexagon::MUX_rr},
- { "MUX_ri", 3, -128, 127, Hexagon::MUX_rr},
- { "MUX_rr", -1, 0, 0, -1},
- { "NEG", -1, 0, 0, -1},
- { "NOP", -1, 0, 0, -1},
- { "NOT_p", -1, 0, 0, -1},
- { "NOT_rr", -1, 0, 0, -1},
- { "NOT_rr64", -1, 0, 0, -1},
- { "OR_pp", -1, 0, 0, -1},
- { "OR_ri", 2, -512, 511, Hexagon::OR_rr},
- { "OR_rr", -1, 0, 0, -1},
- { "OR_rr64", -1, 0, 0, -1},
- { "OR_rr_cNotPt", -1, 0, 0, -1},
- { "OR_rr_cPt", -1, 0, 0, -1},
- { "OR_rr_cdnNotPt", -1, 0, 0, -1},
- { "OR_rr_cdnPt", -1, 0, 0, -1},
- { "ORd_NOTd_V4", -1, 0, 0, -1},
- { "ORi_ASLri_V4", 1, 0, 255, -1},
- { "ORi_LSRri_V4", 1, 0, 255, -1},
- { "ORr_ANDr_NOTr_V4", -1, 0, 0, -1},
- { "ORr_ANDri2_V4", 3, -512, 511, Hexagon::ORr_ANDrr_V4},
- { "ORr_ANDri_V4", 3, -512, 511, -1},
- { "ORr_ANDrr_V4", -1, 0, 0, -1},
- { "ORr_ORri_V4", 3, -512, 511, Hexagon::ORr_ORrr_V4},
- { "ORr_ORrr_V4", -1, 0, 0, -1},
- { "ORr_XORrr_V4", -1, 0, 0, -1},
- { "POST_LDrib", -1, 0, 0, -1},
- { "POST_LDrib_cNotPt", -1, 0, 0, -1},
- { "POST_LDrib_cPt", -1, 0, 0, -1},
- { "POST_LDrib_cdnNotPt_V4", -1, 0, 0, -1},
- { "POST_LDrib_cdnPt_V4", -1, 0, 0, -1},
- { "POST_LDrid", -1, 0, 0, -1},
- { "POST_LDrid_cNotPt", -1, 0, 0, -1},
- { "POST_LDrid_cPt", -1, 0, 0, -1},
- { "POST_LDrid_cdnNotPt_V4", -1, 0, 0, -1},
- { "POST_LDrid_cdnPt_V4", -1, 0, 0, -1},
- { "POST_LDrih", -1, 0, 0, -1},
- { "POST_LDrih_cNotPt", -1, 0, 0, -1},
- { "POST_LDrih_cPt", -1, 0, 0, -1},
- { "POST_LDrih_cdnNotPt_V4", -1, 0, 0, -1},
- { "POST_LDrih_cdnPt_V4", -1, 0, 0, -1},
- { "POST_LDriub", -1, 0, 0, -1},
- { "POST_LDriub_cNotPt", -1, 0, 0, -1},
- { "POST_LDriub_cPt", -1, 0, 0, -1},
- { "POST_LDriub_cdnNotPt_V4", -1, 0, 0, -1},
- { "POST_LDriub_cdnPt_V4", -1, 0, 0, -1},
- { "POST_LDriuh", -1, 0, 0, -1},
- { "POST_LDriuh_cNotPt", -1, 0, 0, -1},
- { "POST_LDriuh_cPt", -1, 0, 0, -1},
- { "POST_LDriuh_cdnNotPt_V4", -1, 0, 0, -1},
- { "POST_LDriuh_cdnPt_V4", -1, 0, 0, -1},
- { "POST_LDriw", -1, 0, 0, -1},
- { "POST_LDriw_cNotPt", -1, 0, 0, -1},
- { "POST_LDriw_cPt", -1, 0, 0, -1},
- { "POST_LDriw_cdnNotPt_V4", -1, 0, 0, -1},
- { "POST_LDriw_cdnPt_V4", -1, 0, 0, -1},
- { "POST_STbri", -1, 0, 0, -1},
- { "POST_STbri_cNotPt", -1, 0, 0, -1},
- { "POST_STbri_cNotPt_nv_V4", -1, 0, 0, -1},
- { "POST_STbri_cPt", -1, 0, 0, -1},
- { "POST_STbri_cPt_nv_V4", -1, 0, 0, -1},
- { "POST_STbri_cdnNotPt_V4", -1, 0, 0, -1},
- { "POST_STbri_cdnNotPt_nv_V4", -1, 0, 0, -1},
- { "POST_STbri_cdnPt_V4", -1, 0, 0, -1},
- { "POST_STbri_cdnPt_nv_V4", -1, 0, 0, -1},
- { "POST_STbri_nv_V4", -1, 0, 0, -1},
- { "POST_STdri", -1, 0, 0, -1},
- { "POST_STdri_cNotPt", -1, 0, 0, -1},
- { "POST_STdri_cPt", -1, 0, 0, -1},
- { "POST_STdri_cdnNotPt_V4", -1, 0, 0, -1},
- { "POST_STdri_cdnPt_V4", -1, 0, 0, -1},
- { "POST_SThri", -1, 0, 0, -1},
- { "POST_SThri_cNotPt", -1, 0, 0, -1},
- { "POST_SThri_cNotPt_nv_V4", -1, 0, 0, -1},
- { "POST_SThri_cPt", -1, 0, 0, -1},
- { "POST_SThri_cPt_nv_V4", -1, 0, 0, -1},
- { "POST_SThri_cdnNotPt_V4", -1, 0, 0, -1},
- { "POST_SThri_cdnNotPt_nv_V4", -1, 0, 0, -1},
- { "POST_SThri_cdnPt_V4", -1, 0, 0, -1},
- { "POST_SThri_cdnPt_nv_V4", -1, 0, 0, -1},
- { "POST_SThri_nv_V4", -1, 0, 0, -1},
- { "POST_STwri", -1, 0, 0, -1},
- { "POST_STwri_cNotPt", -1, 0, 0, -1},
- { "POST_STwri_cNotPt_nv_V4", -1, 0, 0, -1},
- { "POST_STwri_cPt", -1, 0, 0, -1},
- { "POST_STwri_cPt_nv_V4", -1, 0, 0, -1},
- { "POST_STwri_cdnNotPt_V4", -1, 0, 0, -1},
- { "POST_STwri_cdnNotPt_nv_V4", -1, 0, 0, -1},
- { "POST_STwri_cdnPt_V4", -1, 0, 0, -1},
- { "POST_STwri_cdnPt_nv_V4", -1, 0, 0, -1},
- { "POST_STwri_nv_V4", -1, 0, 0, -1},
- { "RESTORE_DEALLOC_BEFORE_TAILCALL_V4", -1, 0, 0, -1},
- { "RESTORE_DEALLOC_RET_JMP_V4", -1, 0, 0, -1},
- { "SAVE_REGISTERS_CALL_V4", -1, 0, 0, -1},
- { "SETBIT", -1, 0, 0, -1},
- { "SETBIT_31", -1, 0, 0, -1},
- { "SI_to_SXTHI_asrh", -1, 0, 0, -1},
- { "STb_GP", -1, 0, 0, -1},
- { "STb_GP_V4", -1, 0, 0, -1},
- { "STb_GP_cNotPt_V4", -1, 0, 0, -1},
- { "STb_GP_cNotPt_nv_V4", -1, 0, 0, -1},
- { "STb_GP_cPt_V4", -1, 0, 0, -1},
- { "STb_GP_cPt_nv_V4", -1, 0, 0, -1},
- { "STb_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "STb_GP_cdnNotPt_nv_V4", -1, 0, 0, -1},
- { "STb_GP_cdnPt_V4", -1, 0, 0, -1},
- { "STb_GP_cdnPt_nv_V4", -1, 0, 0, -1},
- { "STb_GP_nv_V4", -1, 0, 0, -1},
- { "STd_GP", -1, 0, 0, -1},
- { "STd_GP_V4", -1, 0, 0, -1},
- { "STd_GP_cNotPt_V4", -1, 0, 0, -1},
- { "STd_GP_cPt_V4", -1, 0, 0, -1},
- { "STd_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "STd_GP_cdnPt_V4", -1, 0, 0, -1},
- { "STh_GP", -1, 0, 0, -1},
- { "STh_GP_V4", -1, 0, 0, -1},
- { "STh_GP_cNotPt_V4", -1, 0, 0, -1},
- { "STh_GP_cNotPt_nv_V4", -1, 0, 0, -1},
- { "STh_GP_cPt_V4", -1, 0, 0, -1},
- { "STh_GP_cPt_nv_V4", -1, 0, 0, -1},
- { "STh_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "STh_GP_cdnNotPt_nv_V4", -1, 0, 0, -1},
- { "STh_GP_cdnPt_V4", -1, 0, 0, -1},
- { "STh_GP_cdnPt_nv_V4", -1, 0, 0, -1},
- { "STh_GP_nv_V4", -1, 0, 0, -1},
- { "STrib", 1, -1024, 1023, Hexagon::STrib_indexed_shl_V4},
- { "STrib_GP", -1, 0, 0, -1},
- { "STrib_GP_V4", -1, 0, 0, -1},
- { "STrib_GP_cNotPt_V4", -1, 0, 0, -1},
- { "STrib_GP_cNotPt_nv_V4", -1, 0, 0, -1},
- { "STrib_GP_cPt_V4", -1, 0, 0, -1},
- { "STrib_GP_cPt_nv_V4", -1, 0, 0, -1},
- { "STrib_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "STrib_GP_cdnNotPt_nv_V4", -1, 0, 0, -1},
- { "STrib_GP_cdnPt_V4", -1, 0, 0, -1},
- { "STrib_GP_cdnPt_nv_V4", -1, 0, 0, -1},
- { "STrib_GP_nv_V4", -1, 0, 0, -1},
- { "STrib_abs_V4", 0, 0, 0, Hexagon::STrib_indexed},
- { "STrib_abs_cNotPt_V4", 1, 0, 0, Hexagon::STrib_indexed_cNotPt},
- { "STrib_abs_cNotPt_nv_V4", 1, 0, 0, Hexagon::STrib_indexed_cNotPt_nv_V4},
- { "STrib_abs_cPt_V4", 1, 0, 0, Hexagon::STrib_indexed_cPt},
- { "STrib_abs_cPt_nv_V4", 1, 0, 0, Hexagon::STrib_indexed_cPt_nv_V4},
- { "STrib_abs_cdnNotPt_V4", 1, 0, 0, Hexagon::STrib_indexed_cdnNotPt_V4},
- { "STrib_abs_cdnNotPt_nv_V4", 1, 0, 0, Hexagon::STrib_indexed_cdnNotPt_nv_V4},
- { "STrib_abs_cdnPt_V4", 1, 0, 0, Hexagon::STrib_indexed_cdnPt_V4},
- { "STrib_abs_cdnPt_nv_V4", 1, 0, 0, Hexagon::STrib_indexed_cdnPt_nv_V4},
- { "STrib_abs_nv_V4", 0, 0, 0, Hexagon::STrib_indexed_nv_V4},
- { "STrib_abs_set_V4", 2, 0, 0, -1},
- { "STrib_abs_setimm_V4", 2, 0, 63, -1},
- { "STrib_cNotPt", 2, -1024, 1023, Hexagon::STrib_indexed_shl_cNotPt_V4},
- { "STrib_cNotPt_nv_V4", 2, -1024, 1023, Hexagon::STrib_indexed_shl_cNotPt_nv_V4},
- { "STrib_cPt", 2, -1024, 1023, Hexagon::STrib_indexed_shl_cPt_V4},
- { "STrib_cPt_nv_V4", 2, -1024, 1023, Hexagon::STrib_indexed_shl_cPt_nv_V4},
- { "STrib_cdnNotPt_V4", 2, -1024, 1023, Hexagon::STrib_indexed_shl_cdnNotPt_V4},
- { "STrib_cdnNotPt_nv_V4", 2, -1024, 1023, Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4},
- { "STrib_cdnPt_V4", 2, -1024, 1023, Hexagon::STrib_indexed_shl_cdnPt_V4},
- { "STrib_cdnPt_nv_V4", 2, -1024, 1023, Hexagon::STrib_indexed_shl_cdnPt_nv_V4},
- { "STrib_imm_V4", 2, -128, 127, Hexagon::STrib_indexed},
- { "STrib_imm_abs_V4", 0, 0, 63, Hexagon::STrib_indexed},
- { "STrib_imm_abs_cNotPt_V4", 1, 0, 63, Hexagon::STrib_indexed_cNotPt},
- { "STrib_imm_abs_cNotPt_nv_V4", 1, 0, 63, Hexagon::STrib_indexed_cNotPt_nv_V4},
- { "STrib_imm_abs_cPt_V4", 1, 0, 63, Hexagon::STrib_indexed_cPt},
- { "STrib_imm_abs_cPt_nv_V4", 1, 0, 63, Hexagon::STrib_indexed_cPt_nv_V4},
- { "STrib_imm_abs_cdnNotPt_V4", 1, 0, 63, Hexagon::STrib_indexed_cdnNotPt_V4},
- { "STrib_imm_abs_cdnNotPt_nv_V4", 1, 0, 63, Hexagon::STrib_indexed_cdnNotPt_nv_V4},
- { "STrib_imm_abs_cdnPt_V4", 1, 0, 63, Hexagon::STrib_indexed_cdnPt_V4},
- { "STrib_imm_abs_cdnPt_nv_V4", 1, 0, 63, Hexagon::STrib_indexed_cdnPt_nv_V4},
- { "STrib_imm_abs_nv_V4", 0, 0, 63, Hexagon::STrib_indexed_nv_V4},
- { "STrib_imm_cNotPt_V4", 3, -32, 31, Hexagon::STrib_indexed_cNotPt},
- { "STrib_imm_cPt_V4", 3, -32, 31, Hexagon::STrib_indexed_cPt},
- { "STrib_imm_cdnNotPt_V4", 3, -32, 31, Hexagon::STrib_indexed_cdnNotPt_V4},
- { "STrib_imm_cdnPt_V4", 3, -32, 31, Hexagon::STrib_indexed_cdnPt_V4},
- { "STrib_ind_lo_V4", 2, 0, 0, -1},
- { "STrib_indexed", 1, -1024, 1023, Hexagon::STrib_indexed_shl_V4},
- { "STrib_indexed_cNotPt", 2, 0, 63, Hexagon::STrib_indexed_shl_cNotPt_V4},
- { "STrib_indexed_cNotPt_nv_V4", 2, 0, 63, Hexagon::STrib_indexed_shl_cNotPt_nv_V4},
- { "STrib_indexed_cPt", 2, 0, 63, Hexagon::STrib_indexed_shl_cPt_V4},
- { "STrib_indexed_cPt_nv_V4", 2, 0, 63, Hexagon::STrib_indexed_shl_cPt_nv_V4},
- { "STrib_indexed_cdnNotPt_V4", 2, 0, 63, Hexagon::STrib_indexed_shl_cdnNotPt_V4},
- { "STrib_indexed_cdnNotPt_nv_V4", 2, 0, 63, Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4},
- { "STrib_indexed_cdnPt_V4", 2, 0, 63, Hexagon::STrib_indexed_shl_cdnPt_V4},
- { "STrib_indexed_cdnPt_nv_V4", 2, 0, 63, Hexagon::STrib_indexed_shl_cdnPt_nv_V4},
- { "STrib_indexed_nv_V4", 1, -1024, 1023, Hexagon::STrib_indexed_shl_nv_V4},
- { "STrib_indexed_shl_V4", -1, 0, 0, -1},
- { "STrib_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
- { "STrib_indexed_shl_cNotPt_nv_V4", -1, 0, 0, -1},
- { "STrib_indexed_shl_cPt_V4", -1, 0, 0, -1},
- { "STrib_indexed_shl_cPt_nv_V4", -1, 0, 0, -1},
- { "STrib_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
- { "STrib_indexed_shl_cdnNotPt_nv_V4", -1, 0, 0, -1},
- { "STrib_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
- { "STrib_indexed_shl_cdnPt_nv_V4", -1, 0, 0, -1},
- { "STrib_indexed_shl_nv_V4", -1, 0, 0, -1},
- { "STrib_nv_V4", 1, -1024, 1023, Hexagon::STrib_indexed_shl_nv_V4},
- { "STrib_shl_V4", 2, 0, 63, -1},
- { "STrib_shl_nv_V4", 2, 0, 63, -1},
- { "STrid", 1, -8192, 8184, Hexagon::STrid_indexed_shl_V4},
- { "STrid_GP", -1, 0, 0, -1},
- { "STrid_GP_V4", -1, 0, 0, -1},
- { "STrid_GP_cNotPt_V4", -1, 0, 0, -1},
- { "STrid_GP_cPt_V4", -1, 0, 0, -1},
- { "STrid_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "STrid_GP_cdnPt_V4", -1, 0, 0, -1},
- { "STrid_abs_V4", 0, 0, 0, Hexagon::STrid_indexed},
- { "STrid_abs_cNotPt_V4", 1, 0, 0, Hexagon::STrid_indexed_cNotPt},
- { "STrid_abs_cPt_V4", 1, 0, 0, Hexagon::STrid_indexed_cPt},
- { "STrid_abs_cdnNotPt_V4", 1, 0, 0, Hexagon::STrid_indexed_cdnNotPt_V4},
- { "STrid_abs_cdnPt_V4", 1, 0, 0, Hexagon::STrid_indexed_cdnPt_V4},
- { "STrid_abs_set_V4", 2, 0, 0, -1},
- { "STrid_abs_setimm_V4", 2, 0, 63, -1},
- { "STrid_cNotPt", 2, -8192, 8184, Hexagon::STrid_indexed_shl_cNotPt_V4},
- { "STrid_cPt", 2, -8192, 8184, Hexagon::STrid_indexed_shl_cPt_V4},
- { "STrid_cdnNotPt_V4", 2, -8192, 8184, Hexagon::STrid_indexed_shl_cdnNotPt_V4},
- { "STrid_cdnPt_V4", 2, -8192, 8184, Hexagon::STrid_indexed_shl_cdnPt_V4},
- { "STrid_f", 1, -8192, 8184, Hexagon::STrid_indexed_shl_V4},
- { "STrid_ind_lo_V4", 2, 0, 0, -1},
- { "STrid_indexed", 1, -8192, 8184, Hexagon::STrid_indexed_shl_V4},
- { "STrid_indexed_cNotPt", 2, 0, 504, Hexagon::STrid_indexed_shl_cNotPt_V4},
- { "STrid_indexed_cPt", 2, 0, 504, Hexagon::STrid_indexed_shl_cPt_V4},
- { "STrid_indexed_cdnNotPt_V4", 2, 0, 504, Hexagon::STrid_indexed_shl_cdnNotPt_V4},
- { "STrid_indexed_cdnPt_V4", 2, 0, 504, Hexagon::STrid_indexed_shl_cdnPt_V4},
- { "STrid_indexed_f", 1, -8192, 8184, Hexagon::STrid_indexed_shl_V4},
- { "STrid_indexed_shl_V4", -1, 0, 0, -1},
- { "STrid_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
- { "STrid_indexed_shl_cPt_V4", -1, 0, 0, -1},
- { "STrid_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
- { "STrid_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
- { "STrid_shl_V4", 2, 0, 63, -1},
- { "STrih", 1, -2048, 2046, Hexagon::STrih_indexed_shl_V4},
- { "STrih_GP", -1, 0, 0, -1},
- { "STrih_GP_V4", -1, 0, 0, -1},
- { "STrih_GP_cNotPt_V4", -1, 0, 0, -1},
- { "STrih_GP_cNotPt_nv_V4", -1, 0, 0, -1},
- { "STrih_GP_cPt_V4", -1, 0, 0, -1},
- { "STrih_GP_cPt_nv_V4", -1, 0, 0, -1},
- { "STrih_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "STrih_GP_cdnNotPt_nv_V4", -1, 0, 0, -1},
- { "STrih_GP_cdnPt_V4", -1, 0, 0, -1},
- { "STrih_GP_cdnPt_nv_V4", -1, 0, 0, -1},
- { "STrih_GP_nv_V4", -1, 0, 0, -1},
- { "STrih_abs_V4", 0, 0, 0, Hexagon::STrih_indexed},
- { "STrih_abs_cNotPt_V4", 1, 0, 0, Hexagon::STrih_indexed_cNotPt},
- { "STrih_abs_cNotPt_nv_V4", 1, 0, 0, Hexagon::STrih_indexed_cNotPt_nv_V4},
- { "STrih_abs_cPt_V4", 1, 0, 0, Hexagon::STrih_indexed_cPt},
- { "STrih_abs_cPt_nv_V4", 1, 0, 0, Hexagon::STrih_indexed_cPt_nv_V4},
- { "STrih_abs_cdnNotPt_V4", 1, 0, 0, Hexagon::STrih_indexed_cdnNotPt_V4},
- { "STrih_abs_cdnNotPt_nv_V4", 1, 0, 0, Hexagon::STrih_indexed_cdnNotPt_nv_V4},
- { "STrih_abs_cdnPt_V4", 1, 0, 0, Hexagon::STrih_indexed_cdnPt_V4},
- { "STrih_abs_cdnPt_nv_V4", 1, 0, 0, Hexagon::STrih_indexed_cdnPt_nv_V4},
- { "STrih_abs_nv_V4", 0, 0, 0, Hexagon::STrih_indexed_nv_V4},
- { "STrih_abs_set_V4", 2, 0, 0, -1},
- { "STrih_abs_setimm_V4", 2, 0, 63, -1},
- { "STrih_cNotPt", 2, -2048, 2046, Hexagon::STrih_indexed_shl_cNotPt_V4},
- { "STrih_cNotPt_nv_V4", 2, -2048, 2046, Hexagon::STrih_indexed_shl_cNotPt_nv_V4},
- { "STrih_cPt", 2, -2048, 2046, Hexagon::STrih_indexed_shl_cPt_V4},
- { "STrih_cPt_nv_V4", 2, -2048, 2046, Hexagon::STrih_indexed_shl_cPt_nv_V4},
- { "STrih_cdnNotPt_V4", 2, -2048, 2046, Hexagon::STrih_indexed_shl_cdnNotPt_V4},
- { "STrih_cdnNotPt_nv_V4", 2, -2048, 2046, Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4},
- { "STrih_cdnPt_V4", 2, -2048, 2046, Hexagon::STrih_indexed_shl_cdnPt_V4},
- { "STrih_cdnPt_nv_V4", 2, -2048, 2046, Hexagon::STrih_indexed_shl_cdnPt_nv_V4},
- { "STrih_imm_V4", 2, -128, 127, Hexagon::STrih_indexed},
- { "STrih_imm_abs_V4", 0, 0, 63, Hexagon::STrih_indexed},
- { "STrih_imm_abs_cNotPt_V4", 1, 0, 63, Hexagon::STrih_indexed_cNotPt},
- { "STrih_imm_abs_cNotPt_nv_V4", 1, 0, 63, Hexagon::STrih_indexed_cNotPt_nv_V4},
- { "STrih_imm_abs_cPt_V4", 1, 0, 63, Hexagon::STrih_indexed_cPt},
- { "STrih_imm_abs_cPt_nv_V4", 1, 0, 63, Hexagon::STrih_indexed_cPt_nv_V4},
- { "STrih_imm_abs_cdnNotPt_V4", 1, 0, 63, Hexagon::STrih_indexed_cdnNotPt_V4},
- { "STrih_imm_abs_cdnNotPt_nv_V4", 1, 0, 63, Hexagon::STrih_indexed_cdnNotPt_nv_V4},
- { "STrih_imm_abs_cdnPt_V4", 1, 0, 63, Hexagon::STrih_indexed_cdnPt_V4},
- { "STrih_imm_abs_cdnPt_nv_V4", 1, 0, 63, Hexagon::STrih_indexed_cdnPt_nv_V4},
- { "STrih_imm_abs_nv_V4", 0, 0, 63, Hexagon::STrih_indexed_nv_V4},
- { "STrih_imm_cNotPt_V4", 3, -32, 31, Hexagon::STrih_indexed_cNotPt},
- { "STrih_imm_cPt_V4", 3, -32, 31, Hexagon::STrih_indexed_cPt},
- { "STrih_imm_cdnNotPt_V4", 3, -32, 31, Hexagon::STrih_indexed_cdnNotPt_V4},
- { "STrih_imm_cdnPt_V4", 3, -32, 31, Hexagon::STrih_indexed_cdnPt_V4},
- { "STrih_ind_lo_V4", 2, 0, 0, -1},
- { "STrih_indexed", 1, -2048, 2046, Hexagon::STrih_indexed_shl_V4},
- { "STrih_indexed_cNotPt", 2, 0, 126, Hexagon::STrih_indexed_shl_cNotPt_V4},
- { "STrih_indexed_cNotPt_nv_V4", 2, 0, 126, Hexagon::STrih_indexed_shl_cNotPt_nv_V4},
- { "STrih_indexed_cPt", 2, 0, 126, Hexagon::STrih_indexed_shl_cPt_V4},
- { "STrih_indexed_cPt_nv_V4", 2, 0, 126, Hexagon::STrih_indexed_shl_cPt_nv_V4},
- { "STrih_indexed_cdnNotPt_V4", 2, 0, 126, Hexagon::STrih_indexed_shl_cdnNotPt_V4},
- { "STrih_indexed_cdnNotPt_nv_V4", 2, 0, 126, Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4},
- { "STrih_indexed_cdnPt_V4", 2, 0, 126, Hexagon::STrih_indexed_shl_cdnPt_V4},
- { "STrih_indexed_cdnPt_nv_V4", 2, 0, 126, Hexagon::STrih_indexed_shl_cdnPt_nv_V4},
- { "STrih_indexed_nv_V4", 1, -2048, 2046, Hexagon::STrih_indexed_shl_nv_V4},
- { "STrih_indexed_shl_V4", -1, 0, 0, -1},
- { "STrih_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
- { "STrih_indexed_shl_cNotPt_nv_V4", -1, 0, 0, -1},
- { "STrih_indexed_shl_cPt_V4", -1, 0, 0, -1},
- { "STrih_indexed_shl_cPt_nv_V4", -1, 0, 0, -1},
- { "STrih_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
- { "STrih_indexed_shl_cdnNotPt_nv_V4", -1, 0, 0, -1},
- { "STrih_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
- { "STrih_indexed_shl_cdnPt_nv_V4", -1, 0, 0, -1},
- { "STrih_indexed_shl_nv_V4", -1, 0, 0, -1},
- { "STrih_nv_V4", 1, -2048, 2046, Hexagon::STrih_indexed_shl_nv_V4},
- { "STrih_offset_ext_V4", 2, 0, 0, Hexagon::STrih_indexed},
- { "STrih_shl_V4", 2, 0, 63, -1},
- { "STrih_shl_nv_V4", 2, 0, 63, -1},
- { "STriw", 1, -4096, 4092, Hexagon::STriw_indexed_shl_V4},
- { "STriw_GP", -1, 0, 0, -1},
- { "STriw_GP_V4", -1, 0, 0, -1},
- { "STriw_GP_cNotPt_V4", -1, 0, 0, -1},
- { "STriw_GP_cNotPt_nv_V4", -1, 0, 0, -1},
- { "STriw_GP_cPt_V4", -1, 0, 0, -1},
- { "STriw_GP_cPt_nv_V4", -1, 0, 0, -1},
- { "STriw_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "STriw_GP_cdnNotPt_nv_V4", -1, 0, 0, -1},
- { "STriw_GP_cdnPt_V4", -1, 0, 0, -1},
- { "STriw_GP_cdnPt_nv_V4", -1, 0, 0, -1},
- { "STriw_GP_nv_V4", -1, 0, 0, -1},
- { "STriw_abs_V4", 0, 0, 0, Hexagon::STriw_indexed},
- { "STriw_abs_cNotPt_V4", 1, 0, 0, Hexagon::STriw_indexed_cNotPt},
- { "STriw_abs_cNotPt_nv_V4", 1, 0, 0, Hexagon::STriw_indexed_cNotPt_nv_V4},
- { "STriw_abs_cPt_V4", 1, 0, 0, Hexagon::STriw_indexed_cPt},
- { "STriw_abs_cPt_nv_V4", 1, 0, 0, Hexagon::STriw_indexed_cPt_nv_V4},
- { "STriw_abs_cdnNotPt_V4", 1, 0, 0, Hexagon::STriw_indexed_cdnNotPt_V4},
- { "STriw_abs_cdnNotPt_nv_V4", 1, 0, 0, Hexagon::STriw_indexed_cdnNotPt_nv_V4},
- { "STriw_abs_cdnPt_V4", 1, 0, 0, Hexagon::STriw_indexed_cdnPt_V4},
- { "STriw_abs_cdnPt_nv_V4", 1, 0, 0, Hexagon::STriw_indexed_cdnPt_nv_V4},
- { "STriw_abs_nv_V4", 0, 0, 0, Hexagon::STriw_indexed_nv_V4},
- { "STriw_abs_set_V4", 2, 0, 0, -1},
- { "STriw_abs_setimm_V4", 2, 0, 63, -1},
- { "STriw_cNotPt", 2, -4096, 4092, Hexagon::STriw_indexed_shl_cNotPt_V4},
- { "STriw_cNotPt_nv_V4", 2, -4096, 4092, Hexagon::STriw_indexed_shl_cNotPt_nv_V4},
- { "STriw_cPt", 2, -4096, 4092, Hexagon::STriw_indexed_shl_cPt_V4},
- { "STriw_cPt_nv_V4", 2, -4096, 4092, Hexagon::STriw_indexed_shl_cPt_nv_V4},
- { "STriw_cdnNotPt_V4", 2, -4096, 4092, Hexagon::STriw_indexed_shl_cdnNotPt_V4},
- { "STriw_cdnNotPt_nv_V4", 2, -4096, 4092, Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4},
- { "STriw_cdnPt_V4", 2, -4096, 4092, Hexagon::STriw_indexed_shl_cdnPt_V4},
- { "STriw_cdnPt_nv_V4", 2, -4096, 4092, Hexagon::STriw_indexed_shl_cdnPt_nv_V4},
- { "STriw_f", 1, -4096, 4092, Hexagon::STriw_indexed_shl_V4},
- { "STriw_imm_V4", 2, -128, 127, Hexagon::STriw_indexed},
- { "STriw_imm_abs_V4", 0, 0, 63, Hexagon::STriw_indexed},
- { "STriw_imm_abs_cNotPt_V4", 1, 0, 63, Hexagon::STriw_indexed_cNotPt},
- { "STriw_imm_abs_cNotPt_nv_V4", 1, 0, 63, Hexagon::STriw_indexed_cNotPt_nv_V4},
- { "STriw_imm_abs_cPt_V4", 1, 0, 63, Hexagon::STriw_indexed_cPt},
- { "STriw_imm_abs_cPt_nv_V4", 1, 0, 63, Hexagon::STriw_indexed_cPt_nv_V4},
- { "STriw_imm_abs_cdnNotPt_V4", 1, 0, 63, Hexagon::STriw_indexed_cdnNotPt_V4},
- { "STriw_imm_abs_cdnNotPt_nv_V4", 1, 0, 63, Hexagon::STriw_indexed_cdnNotPt_nv_V4},
- { "STriw_imm_abs_cdnPt_V4", 1, 0, 63, Hexagon::STriw_indexed_cdnPt_V4},
- { "STriw_imm_abs_cdnPt_nv_V4", 1, 0, 63, Hexagon::STriw_indexed_cdnPt_nv_V4},
- { "STriw_imm_abs_nv_V4", 0, 0, 63, Hexagon::STriw_indexed_nv_V4},
- { "STriw_imm_cNotPt_V4", 3, -32, 31, Hexagon::STriw_indexed_cNotPt},
- { "STriw_imm_cPt_V4", 3, -32, 31, Hexagon::STriw_indexed_cPt},
- { "STriw_imm_cdnNotPt_V4", 3, -32, 31, Hexagon::STriw_indexed_cdnNotPt_V4},
- { "STriw_imm_cdnPt_V4", 3, -32, 31, Hexagon::STriw_indexed_cdnPt_V4},
- { "STriw_ind_lo_V4", 2, 0, 0, -1},
- { "STriw_indexed", 1, -4096, 4092, Hexagon::STriw_indexed_shl_V4},
- { "STriw_indexed_cNotPt", 2, 0, 252, Hexagon::STriw_indexed_shl_cNotPt_V4},
- { "STriw_indexed_cNotPt_nv_V4", 2, 0, 252, Hexagon::STriw_indexed_shl_cNotPt_nv_V4},
- { "STriw_indexed_cPt", 2, 0, 252, Hexagon::STriw_indexed_shl_cPt_V4},
- { "STriw_indexed_cPt_nv_V4", 2, 0, 252, Hexagon::STriw_indexed_shl_cPt_nv_V4},
- { "STriw_indexed_cdnNotPt_V4", 2, 0, 252, Hexagon::STriw_indexed_shl_cdnNotPt_V4},
- { "STriw_indexed_cdnNotPt_nv_V4", 2, 0, 252, Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4},
- { "STriw_indexed_cdnPt_V4", 2, 0, 252, Hexagon::STriw_indexed_shl_cdnPt_V4},
- { "STriw_indexed_cdnPt_nv_V4", 2, 0, 252, Hexagon::STriw_indexed_shl_cdnPt_nv_V4},
- { "STriw_indexed_f", 1, -4096, 4092, Hexagon::STriw_indexed_shl_V4},
- { "STriw_indexed_nv_V4", 1, -4096, 4092, Hexagon::STriw_indexed_shl_nv_V4},
- { "STriw_indexed_shl_V4", -1, 0, 0, -1},
- { "STriw_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
- { "STriw_indexed_shl_cNotPt_nv_V4", -1, 0, 0, -1},
- { "STriw_indexed_shl_cPt_V4", -1, 0, 0, -1},
- { "STriw_indexed_shl_cPt_nv_V4", -1, 0, 0, -1},
- { "STriw_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
- { "STriw_indexed_shl_cdnNotPt_nv_V4", -1, 0, 0, -1},
- { "STriw_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
- { "STriw_indexed_shl_cdnPt_nv_V4", -1, 0, 0, -1},
- { "STriw_indexed_shl_nv_V4", -1, 0, 0, -1},
- { "STriw_nv_V4", 1, -4096, 4092, Hexagon::STriw_indexed_shl_nv_V4},
- { "STriw_offset_ext_V4", 2, 0, 0, Hexagon::STriw_indexed},
- { "STriw_pred", 1, -4096, 4092, -1},
- { "STriw_pred_V4", 1, -4096, 4092, -1},
- { "STriw_shl_V4", 2, 0, 63, -1},
- { "STriw_shl_nv_V4", 2, 0, 63, -1},
- { "STw_GP", -1, 0, 0, -1},
- { "STw_GP_V4", -1, 0, 0, -1},
- { "STw_GP_cNotPt_V4", -1, 0, 0, -1},
- { "STw_GP_cNotPt_nv_V4", -1, 0, 0, -1},
- { "STw_GP_cPt_V4", -1, 0, 0, -1},
- { "STw_GP_cPt_nv_V4", -1, 0, 0, -1},
- { "STw_GP_cdnNotPt_V4", -1, 0, 0, -1},
- { "STw_GP_cdnNotPt_nv_V4", -1, 0, 0, -1},
- { "STw_GP_cdnPt_V4", -1, 0, 0, -1},
- { "STw_GP_cdnPt_nv_V4", -1, 0, 0, -1},
- { "STw_GP_nv_V4", -1, 0, 0, -1},
- { "SUB64_rr", -1, 0, 0, -1},
- { "SUB_ri", 1, -512, 511, Hexagon::SUB_rr},
- { "SUB_rr", -1, 0, 0, -1},
- { "SUB_rr_cNotPt", -1, 0, 0, -1},
- { "SUB_rr_cPt", -1, 0, 0, -1},
- { "SUB_rr_cdnNotPt", -1, 0, 0, -1},
- { "SUB_rr_cdnPt", -1, 0, 0, -1},
- { "SUBi_ASLri_V4", 1, 0, 255, -1},
- { "SUBi_LSRri_V4", 1, 0, 255, -1},
- { "SUBri_acc", 3, -128, 127, Hexagon::SUBrr_acc},
- { "SUBrr_acc", -1, 0, 0, -1},
- { "SXTB", -1, 0, 0, -1},
- { "SXTB_cNotPt_V4", -1, 0, 0, -1},
- { "SXTB_cPt_V4", -1, 0, 0, -1},
- { "SXTB_cdnNotPt_V4", -1, 0, 0, -1},
- { "SXTB_cdnPt_V4", -1, 0, 0, -1},
- { "SXTH", -1, 0, 0, -1},
- { "SXTH_cNotPt_V4", -1, 0, 0, -1},
- { "SXTH_cPt_V4", -1, 0, 0, -1},
- { "SXTH_cdnNotPt_V4", -1, 0, 0, -1},
- { "SXTH_cdnPt_V4", -1, 0, 0, -1},
- { "SXTW", -1, 0, 0, -1},
- { "TCRETURNR", -1, 0, 0, -1},
- { "TCRETURNtext", -1, 0, 0, -1},
- { "TCRETURNtg", -1, 0, 0, -1},
- { "TFCR", -1, 0, 0, -1},
- { "TFR", -1, 0, 0, -1},
- { "TFR64", -1, 0, 0, -1},
- { "TFR64_cNotPt", -1, 0, 0, -1},
- { "TFR64_cPt", -1, 0, 0, -1},
- { "TFRI", 1, -32768, 32767, Hexagon::TFR},
- { "TFRI64", -1, 0, 0, -1},
- { "TFRI_V4", 1, 0, 0, -1},
- { "TFRI_cNotPt", 2, -2048, 2047, Hexagon::TFR_cNotPt},
- { "TFRI_cNotPt_V4", 2, 0, 0, -1},
- { "TFRI_cNotPt_f", 2, 0, 0, -1},
- { "TFRI_cPt", 2, -2048, 2047, Hexagon::TFR_cPt},
- { "TFRI_cPt_V4", 2, 0, 0, -1},
- { "TFRI_cPt_f", 2, 0, 0, -1},
- { "TFRI_cdnNotPt", 2, -2048, 2047, Hexagon::TFR_cdnNotPt},
- { "TFRI_cdnNotPt_V4", 2, 0, 0, -1},
- { "TFRI_cdnPt", 2, -2048, 2047, Hexagon::TFR_cdnPt},
- { "TFRI_cdnPt_V4", 2, 0, 0, -1},
- { "TFRI_f", 1, 0, 0, -1},
- { "TFR_64", -1, 0, 0, -1},
- { "TFR_FI", -1, 0, 0, -1},
- { "TFR_FI_immext_V4", -1, 0, 0, -1},
- { "TFR_PdFalse", -1, 0, 0, -1},
- { "TFR_PdRs", -1, 0, 0, -1},
- { "TFR_RsPd", -1, 0, 0, -1},
- { "TFR_cNotPt", -1, 0, 0, -1},
- { "TFR_cPt", -1, 0, 0, -1},
- { "TFR_cdnNotPt", -1, 0, 0, -1},
- { "TFR_cdnPt", -1, 0, 0, -1},
- { "TFR_condset_ii", -1, 0, 0, -1},
- { "TFR_condset_ii_f", -1, 0, 0, -1},
- { "TFR_condset_ir", -1, 0, 0, -1},
- { "TFR_condset_ir_f", -1, 0, 0, -1},
- { "TFR_condset_ri", -1, 0, 0, -1},
- { "TFR_condset_ri_f", -1, 0, 0, -1},
- { "TFR_condset_rr", -1, 0, 0, -1},
- { "TFR_condset_rr64_f", -1, 0, 0, -1},
- { "TFR_condset_rr_f", -1, 0, 0, -1},
- { "TOGBIT", -1, 0, 0, -1},
- { "TOGBIT_31", -1, 0, 0, -1},
- { "VALIGN_rrp", -1, 0, 0, -1},
- { "VITPACK_pp", -1, 0, 0, -1},
- { "VMUX_prr64", -1, 0, 0, -1},
- { "VSPLICE_rrp", -1, 0, 0, -1},
- { "XOR_pp", -1, 0, 0, -1},
- { "XOR_rr", -1, 0, 0, -1},
- { "XOR_rr64", -1, 0, 0, -1},
- { "XOR_rr_cNotPt", -1, 0, 0, -1},
- { "XOR_rr_cPt", -1, 0, 0, -1},
- { "XOR_rr_cdnNotPt", -1, 0, 0, -1},
- { "XOR_rr_cdnPt", -1, 0, 0, -1},
- { "XORd_XORdd", -1, 0, 0, -1},
- { "XORr_ANDr_NOTr_V4", -1, 0, 0, -1},
- { "XORr_ANDrr_V4", -1, 0, 0, -1},
- { "XORr_ORrr_V4", -1, 0, 0, -1},
- { "XORr_XORrr_V4", -1, 0, 0, -1},
- { "ZXTB", -1, 0, 0, -1},
- { "ZXTB_cNotPt_V4", -1, 0, 0, -1},
- { "ZXTB_cPt_V4", -1, 0, 0, -1},
- { "ZXTB_cdnNotPt_V4", -1, 0, 0, -1},
- { "ZXTB_cdnPt_V4", -1, 0, 0, -1},
- { "ZXTH", -1, 0, 0, -1},
- { "ZXTH_cNotPt_V4", -1, 0, 0, -1},
- { "ZXTH_cPt_V4", -1, 0, 0, -1},
- { "ZXTH_cdnNotPt_V4", -1, 0, 0, -1},
- { "ZXTH_cdnPt_V4", -1, 0, 0, -1},
- { "fADD64_rr", -1, 0, 0, -1},
- { "fADD_rr", -1, 0, 0, -1},
- { "fMUL64_rr", -1, 0, 0, -1},
- { "fMUL_rr", -1, 0, 0, -1},
- { "fSUB64_rr", -1, 0, 0, -1},
- { "fSUB_rr", -1, 0, 0, -1},
- { "INSTRUCTION_LIST_END", -1, 0, 0, -1},
- };
-
-#endif
let neverHasSideEffects = 1 in
def LDrid_abs_setimm_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
- (ins u6Ext:$addr),
+ (ins u6Imm:$addr),
"$dst1 = memd($dst2=#$addr)",
[]>,
Requires<[HasV4T]>;
// Rd=memb(Re=#U6)
let neverHasSideEffects = 1 in
def LDrib_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
- (ins u6Ext:$addr),
+ (ins u6Imm:$addr),
"$dst1 = memb($dst2=#$addr)",
[]>,
Requires<[HasV4T]>;
// Rd=memh(Re=#U6)
let neverHasSideEffects = 1 in
def LDrih_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
- (ins u6Ext:$addr),
+ (ins u6Imm:$addr),
"$dst1 = memh($dst2=#$addr)",
[]>,
Requires<[HasV4T]>;
// Rd=memub(Re=#U6)
let neverHasSideEffects = 1 in
def LDriub_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
- (ins u6Ext:$addr),
+ (ins u6Imm:$addr),
"$dst1 = memub($dst2=#$addr)",
[]>,
Requires<[HasV4T]>;
// Rd=memuh(Re=#U6)
let neverHasSideEffects = 1 in
def LDriuh_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
- (ins u6Ext:$addr),
+ (ins u6Imm:$addr),
"$dst1 = memuh($dst2=#$addr)",
[]>,
Requires<[HasV4T]>;
// Rd=memw(Re=#U6)
let neverHasSideEffects = 1 in
def LDriw_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
- (ins u6Ext:$addr),
+ (ins u6Imm:$addr),
"$dst1 = memw($dst2=#$addr)",
[]>,
Requires<[HasV4T]>;
// instruction which take global address as operand.
let neverHasSideEffects = 1 in
def LDrid_abs_set_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
- (ins globaladdressExt:$addr),
+ (ins globaladdress:$addr),
"$dst1 = memd($dst2=##$addr)",
[]>,
Requires<[HasV4T]>;
// Rd=memb(Re=#U6)
let neverHasSideEffects = 1 in
def LDrib_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
- (ins globaladdressExt:$addr),
+ (ins globaladdress:$addr),
"$dst1 = memb($dst2=##$addr)",
[]>,
Requires<[HasV4T]>;
// Rd=memh(Re=#U6)
let neverHasSideEffects = 1 in
def LDrih_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
- (ins globaladdressExt:$addr),
+ (ins globaladdress:$addr),
"$dst1 = memh($dst2=##$addr)",
[]>,
Requires<[HasV4T]>;
// Rd=memub(Re=#U6)
let neverHasSideEffects = 1 in
def LDriub_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
- (ins globaladdressExt:$addr),
+ (ins globaladdress:$addr),
"$dst1 = memub($dst2=##$addr)",
[]>,
Requires<[HasV4T]>;
// Rd=memuh(Re=#U6)
let neverHasSideEffects = 1 in
def LDriuh_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
- (ins globaladdressExt:$addr),
+ (ins globaladdress:$addr),
"$dst1 = memuh($dst2=##$addr)",
[]>,
Requires<[HasV4T]>;
// Rd=memw(Re=#U6)
let neverHasSideEffects = 1 in
def LDriw_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
- (ins globaladdressExt:$addr),
+ (ins globaladdress:$addr),
"$dst1 = memw($dst2=##$addr)",
[]>,
Requires<[HasV4T]>;
// memd(Re=#U6)=Rtt
def STrid_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
- (ins DoubleRegs:$src1, u6Ext:$src2),
+ (ins DoubleRegs:$src1, u6Imm:$src2),
"memd($dst1=#$src2) = $src1",
[]>,
Requires<[HasV4T]>;
// memb(Re=#U6)=Rs
def STrib_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
- (ins IntRegs:$src1, u6Ext:$src2),
+ (ins IntRegs:$src1, u6Imm:$src2),
"memb($dst1=#$src2) = $src1",
[]>,
Requires<[HasV4T]>;
// memh(Re=#U6)=Rs
def STrih_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
- (ins IntRegs:$src1, u6Ext:$src2),
+ (ins IntRegs:$src1, u6Imm:$src2),
"memh($dst1=#$src2) = $src1",
[]>,
Requires<[HasV4T]>;
// memw(Re=#U6)=Rs
def STriw_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
- (ins IntRegs:$src1, u6Ext:$src2),
+ (ins IntRegs:$src1, u6Imm:$src2),
"memw($dst1=#$src2) = $src1",
[]>,
Requires<[HasV4T]>;
// memd(Re=#U6)=Rtt
def STrid_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
- (ins DoubleRegs:$src1, globaladdressExt:$src2),
+ (ins DoubleRegs:$src1, globaladdress:$src2),
"memd($dst1=##$src2) = $src1",
[]>,
Requires<[HasV4T]>;
// memb(Re=#U6)=Rs
def STrib_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
- (ins IntRegs:$src1, globaladdressExt:$src2),
+ (ins IntRegs:$src1, globaladdress:$src2),
"memb($dst1=##$src2) = $src1",
[]>,
Requires<[HasV4T]>;
// memh(Re=#U6)=Rs
def STrih_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
- (ins IntRegs:$src1, globaladdressExt:$src2),
+ (ins IntRegs:$src1, globaladdress:$src2),
"memh($dst1=##$src2) = $src1",
[]>,
Requires<[HasV4T]>;
// memw(Re=#U6)=Rs
def STriw_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
- (ins IntRegs:$src1, globaladdressExt:$src2),
+ (ins IntRegs:$src1, globaladdress:$src2),
"memw($dst1=##$src2) = $src1",
[]>,
Requires<[HasV4T]>;
// memd(Ru<<#u2+#U6)=Rtt
let AddedComplexity = 10 in
def STrid_shl_V4 : STInst<(outs),
- (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, DoubleRegs:$src4),
+ (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, DoubleRegs:$src4),
"memd($src1<<#$src2+#$src3) = $src4",
[(store (i64 DoubleRegs:$src4),
(add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
- u6ExtPred:$src3))]>,
+ u6ImmPred:$src3))]>,
Requires<[HasV4T]>;
// memd(Rx++#s4:3)=Rtt
let AddedComplexity = 10, neverHasSideEffects = 1,
isPredicated = 1 in
def STrid_indexed_cdnPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_3Ext:$src3,
+ (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
DoubleRegs:$src4),
"if ($src1.new) memd($src2+#$src3) = $src4",
[]>,
let AddedComplexity = 10, neverHasSideEffects = 1,
isPredicated = 1 in
def STrid_indexed_cdnNotPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_3Ext:$src3,
+ (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
DoubleRegs:$src4),
"if (!$src1.new) memd($src2+#$src3) = $src4",
[]>,
// memb(Rs+#u6:0)=#S8
let AddedComplexity = 10, isPredicable = 1 in
def STrib_imm_V4 : STInst<(outs),
- (ins IntRegs:$src1, u6_0Imm:$src2, s8Ext:$src3),
+ (ins IntRegs:$src1, u6_0Imm:$src2, s8Imm:$src3),
"memb($src1+#$src2) = #$src3",
- [(truncstorei8 s8ExtPred:$src3, (add (i32 IntRegs:$src1),
+ [(truncstorei8 s8ImmPred:$src3, (add (i32 IntRegs:$src1),
u6_0ImmPred:$src2))]>,
Requires<[HasV4T]>;
// memb(Ru<<#u2+#U6)=Rt
let AddedComplexity = 10 in
def STrib_shl_V4 : STInst<(outs),
- (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
+ (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
"memb($src1<<#$src2+#$src3) = $src4",
[(truncstorei8 (i32 IntRegs:$src4),
(add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
- u6ExtPred:$src3))]>,
+ u6ImmPred:$src3))]>,
Requires<[HasV4T]>;
// memb(Rx++#s4:0:circ(Mu))=Rt
let neverHasSideEffects = 1,
isPredicated = 1 in
def STrib_imm_cPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Ext:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
"if ($src1) memb($src2+#$src3) = #$src4",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1,
isPredicated = 1 in
def STrib_imm_cdnPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Ext:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
"if ($src1.new) memb($src2+#$src3) = #$src4",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1,
isPredicated = 1 in
def STrib_imm_cNotPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Ext:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
"if (!$src1) memb($src2+#$src3) = #$src4",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1,
isPredicated = 1 in
def STrib_imm_cdnNotPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Ext:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
"if (!$src1.new) memb($src2+#$src3) = #$src4",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1,
isPredicated = 1 in
def STrib_indexed_cdnPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3, IntRegs:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
"if ($src1.new) memb($src2+#$src3) = $src4",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1,
isPredicated = 1 in
def STrib_indexed_cdnNotPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3, IntRegs:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
"if (!$src1.new) memb($src2+#$src3) = $src4",
[]>,
Requires<[HasV4T]>;
// memh(Rs+#u6:1)=#S8
let AddedComplexity = 10, isPredicable = 1 in
def STrih_imm_V4 : STInst<(outs),
- (ins IntRegs:$src1, u6_1Imm:$src2, s8Ext:$src3),
+ (ins IntRegs:$src1, u6_1Imm:$src2, s8Imm:$src3),
"memh($src1+#$src2) = #$src3",
- [(truncstorei16 s8ExtPred:$src3, (add (i32 IntRegs:$src1),
+ [(truncstorei16 s8ImmPred:$src3, (add (i32 IntRegs:$src1),
u6_1ImmPred:$src2))]>,
Requires<[HasV4T]>;
// memh(Ru<<#u2+#U6)=Rt
let AddedComplexity = 10 in
def STrih_shl_V4 : STInst<(outs),
- (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
+ (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
"memh($src1<<#$src2+#$src3) = $src4",
[(truncstorei16 (i32 IntRegs:$src4),
(add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
- u6ExtPred:$src3))]>,
+ u6ImmPred:$src3))]>,
Requires<[HasV4T]>;
// memh(Rx++#s4:1:circ(Mu))=Rt.H
let neverHasSideEffects = 1,
isPredicated = 1 in
def STrih_imm_cPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Ext:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
"if ($src1) memh($src2+#$src3) = #$src4",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1,
isPredicated = 1 in
def STrih_imm_cdnPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Ext:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
"if ($src1.new) memh($src2+#$src3) = #$src4",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1,
isPredicated = 1 in
def STrih_imm_cNotPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Ext:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
"if (!$src1) memh($src2+#$src3) = #$src4",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1,
isPredicated = 1 in
def STrih_imm_cdnNotPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Ext:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
"if (!$src1.new) memh($src2+#$src3) = #$src4",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1,
isPredicated = 1 in
def STrih_indexed_cdnPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3, IntRegs:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
"if ($src1.new) memh($src2+#$src3) = $src4",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1,
isPredicated = 1 in
def STrih_indexed_cdnNotPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3, IntRegs:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
"if (!$src1.new) memh($src2+#$src3) = $src4",
[]>,
Requires<[HasV4T]>;
// memw(Rs+#u6:2)=#S8
let AddedComplexity = 10, isPredicable = 1 in
def STriw_imm_V4 : STInst<(outs),
- (ins IntRegs:$src1, u6_2Imm:$src2, s8Ext:$src3),
+ (ins IntRegs:$src1, u6_2Imm:$src2, s8Imm:$src3),
"memw($src1+#$src2) = #$src3",
- [(store s8ExtPred:$src3, (add (i32 IntRegs:$src1),
+ [(store s8ImmPred:$src3, (add (i32 IntRegs:$src1),
u6_2ImmPred:$src2))]>,
Requires<[HasV4T]>;
// memw(Ru<<#u2+#U6)=Rt
let AddedComplexity = 10 in
def STriw_shl_V4 : STInst<(outs),
- (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
+ (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
"memw($src1<<#$src2+#$src3) = $src4",
[(store (i32 IntRegs:$src4),
(add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
- u6ExtPred:$src3))]>,
+ u6ImmPred:$src3))]>,
Requires<[HasV4T]>;
// memw(Rx++#s4:2)=Rt
let neverHasSideEffects = 1,
isPredicated = 1 in
def STriw_imm_cPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Ext:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
"if ($src1) memw($src2+#$src3) = #$src4",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1,
isPredicated = 1 in
def STriw_imm_cdnPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Ext:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
"if ($src1.new) memw($src2+#$src3) = #$src4",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1,
isPredicated = 1 in
def STriw_imm_cNotPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Ext:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
"if (!$src1) memw($src2+#$src3) = #$src4",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1,
isPredicated = 1 in
def STriw_imm_cdnNotPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Ext:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
"if (!$src1.new) memw($src2+#$src3) = #$src4",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1,
isPredicated = 1 in
def STriw_indexed_cdnPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_2Ext:$src3, IntRegs:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
"if ($src1.new) memw($src2+#$src3) = $src4",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1,
isPredicated = 1 in
def STriw_indexed_cdnNotPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_2Ext:$src3, IntRegs:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
"if (!$src1.new) memw($src2+#$src3) = $src4",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, isPredicable = 1 in
def STrib_indexed_nv_V4 : NVInst_V4<(outs),
- (ins IntRegs:$src1, s11_0Ext:$src2, IntRegs:$src3),
+ (ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
"memb($src1+#$src2) = $src3.new",
[]>,
Requires<[HasV4T]>;
// memb(Ru<<#u2+#U6)=Nt.new
let mayStore = 1, AddedComplexity = 10 in
def STrib_shl_nv_V4 : NVInst_V4<(outs),
- (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
+ (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
"memb($src1<<#$src2+#$src3) = $src4.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1,
isPredicated = 1 in
def STrib_indexed_cPt_nv_V4 : NVInst_V4<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3, IntRegs:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
"if ($src1) memb($src2+#$src3) = $src4.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1,
isPredicated = 1 in
def STrib_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3, IntRegs:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
"if ($src1.new) memb($src2+#$src3) = $src4.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1,
isPredicated = 1 in
def STrib_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3, IntRegs:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
"if (!$src1) memb($src2+#$src3) = $src4.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1,
isPredicated = 1 in
def STrib_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3, IntRegs:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
"if (!$src1.new) memb($src2+#$src3) = $src4.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, isPredicable = 1 in
def STrih_indexed_nv_V4 : NVInst_V4<(outs),
- (ins IntRegs:$src1, s11_1Ext:$src2, IntRegs:$src3),
+ (ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3),
"memh($src1+#$src2) = $src3.new",
[]>,
Requires<[HasV4T]>;
// memh(Ru<<#u2+#U6)=Nt.new
let mayStore = 1, AddedComplexity = 10 in
def STrih_shl_nv_V4 : NVInst_V4<(outs),
- (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
+ (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
"memh($src1<<#$src2+#$src3) = $src4.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1,
isPredicated = 1 in
def STrih_indexed_cPt_nv_V4 : NVInst_V4<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3, IntRegs:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
"if ($src1) memh($src2+#$src3) = $src4.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1,
isPredicated = 1 in
def STrih_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3, IntRegs:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
"if ($src1.new) memh($src2+#$src3) = $src4.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1,
isPredicated = 1 in
def STrih_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3, IntRegs:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
"if (!$src1) memh($src2+#$src3) = $src4.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1,
isPredicated = 1 in
def STrih_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3, IntRegs:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
"if (!$src1.new) memh($src2+#$src3) = $src4.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, isPredicable = 1 in
def STriw_indexed_nv_V4 : NVInst_V4<(outs),
- (ins IntRegs:$src1, s11_2Ext:$src2, IntRegs:$src3),
+ (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
"memw($src1+#$src2) = $src3.new",
[]>,
Requires<[HasV4T]>;
// memw(Ru<<#u2+#U6)=Nt.new
let mayStore = 1, AddedComplexity = 10 in
def STriw_shl_nv_V4 : NVInst_V4<(outs),
- (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
+ (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
"memw($src1<<#$src2+#$src3) = $src4.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1,
isPredicated = 1 in
def STriw_indexed_cPt_nv_V4 : NVInst_V4<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_2Ext:$src3, IntRegs:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
"if ($src1) memw($src2+#$src3) = $src4.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1,
isPredicated = 1 in
def STriw_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_2Ext:$src3, IntRegs:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
"if ($src1.new) memw($src2+#$src3) = $src4.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1,
isPredicated = 1 in
def STriw_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_2Ext:$src3, IntRegs:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
"if (!$src1) memw($src2+#$src3) = $src4.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1,
isPredicated = 1 in
def STriw_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
- (ins PredRegs:$src1, IntRegs:$src2, u6_2Ext:$src3, IntRegs:$src4),
+ (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
"if (!$src1.new) memw($src2+#$src3) = $src4.new",
[]>,
Requires<[HasV4T]>;
// Add and accumulate.
// Rd=add(Rs,add(Ru,#s6))
def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
- (ins IntRegs:$src1, IntRegs:$src2, s6Ext:$src3),
+ (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),
"$dst = add($src1, add($src2, #$src3))",
[(set (i32 IntRegs:$dst),
(add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
- s6_16ExtPred:$src3)))]>,
+ s6ImmPred:$src3)))]>,
Requires<[HasV4T]>;
// Rd=add(Rs,sub(#s6,Ru))
def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
- (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
+ (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
"$dst = add($src1, sub(#$src2, $src3))",
[(set (i32 IntRegs:$dst),
- (add (i32 IntRegs:$src1), (sub s6_10ExtPred:$src2,
+ (add (i32 IntRegs:$src1), (sub s6ImmPred:$src2,
(i32 IntRegs:$src3))))]>,
Requires<[HasV4T]>;
// pattern.
// Rd=add(Rs,sub(#s6,Ru))
def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
- (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
+ (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
"$dst = add($src1, sub(#$src2, $src3))",
[(set (i32 IntRegs:$dst),
- (sub (add (i32 IntRegs:$src1), s6_10ExtPred:$src2),
+ (sub (add (i32 IntRegs:$src1), s6ImmPred:$src2),
(i32 IntRegs:$src3)))]>,
Requires<[HasV4T]>;
// Logical-logical words.
// Rx=or(Ru,and(Rx,#s10))
def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
- (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
+ (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
"$dst = or($src1, and($src2, #$src3))",
[(set (i32 IntRegs:$dst),
(or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
- s10ExtPred:$src3)))],
+ s10ImmPred:$src3)))],
"$src2 = $dst">,
Requires<[HasV4T]>;
// Rx|=and(Rs,#s10)
def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
- (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
+ (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
"$dst |= and($src2, #$src3)",
[(set (i32 IntRegs:$dst),
(or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
- s10ExtPred:$src3)))],
+ s10ImmPred:$src3)))],
"$src1 = $dst">,
Requires<[HasV4T]>;
// Rx|=or(Rs,#s10)
def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
- (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
+ (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
"$dst |= or($src2, #$src3)",
[(set (i32 IntRegs:$dst),
(or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
- s10ExtPred:$src3)))],
+ s10ImmPred:$src3)))],
"$src1 = $dst">,
Requires<[HasV4T]>;
// Multiply and user lower result.
// Rd=add(#u6,mpyi(Rs,#U6))
def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
- (ins u6Ext:$src1, IntRegs:$src2, u6Imm:$src3),
+ (ins u6Imm:$src1, IntRegs:$src2, u6Imm:$src3),
"$dst = add(#$src1, mpyi($src2, #$src3))",
[(set (i32 IntRegs:$dst),
(add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
- u6ExtPred:$src1))]>,
+ u6ImmPred:$src1))]>,
Requires<[HasV4T]>;
// Rd=add(#u6,mpyi(Rs,Rt))
def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
- (ins u6Ext:$src1, IntRegs:$src2, IntRegs:$src3),
+ (ins u6Imm:$src1, IntRegs:$src2, IntRegs:$src3),
"$dst = add(#$src1, mpyi($src2, $src3))",
[(set (i32 IntRegs:$dst),
(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
- u6ExtPred:$src1))]>,
+ u6ImmPred:$src1))]>,
Requires<[HasV4T]>;
// Rd=add(Ru,mpyi(#u6:2,Rs))
// Rd=add(Ru,mpyi(Rs,#u6))
def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
- (ins IntRegs:$src1, IntRegs:$src2, u6Ext:$src3),
+ (ins IntRegs:$src1, IntRegs:$src2, u6Imm:$src3),
"$dst = add($src1, mpyi($src2, #$src3))",
[(set (i32 IntRegs:$dst),
(add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
- u6ExtPred:$src3)))]>,
+ u6ImmPred:$src3)))]>,
Requires<[HasV4T]>;
// Rx=add(Ru,mpyi(Rx,Rs))
// Shift by immediate and accumulate.
// Rx=add(#u8,asl(Rx,#U5))
def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
- (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
+ (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
"$dst = add(#$src1, asl($src2, #$src3))",
[(set (i32 IntRegs:$dst),
(add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
- u8ExtPred:$src1))],
+ u8ImmPred:$src1))],
"$src2 = $dst">,
Requires<[HasV4T]>;
// Rx=add(#u8,lsr(Rx,#U5))
def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
- (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
+ (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
"$dst = add(#$src1, lsr($src2, #$src3))",
[(set (i32 IntRegs:$dst),
(add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
- u8ExtPred:$src1))],
+ u8ImmPred:$src1))],
"$src2 = $dst">,
Requires<[HasV4T]>;
// Rx=sub(#u8,asl(Rx,#U5))
def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
- (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
+ (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
"$dst = sub(#$src1, asl($src2, #$src3))",
[(set (i32 IntRegs:$dst),
(sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
- u8ExtPred:$src1))],
+ u8ImmPred:$src1))],
"$src2 = $dst">,
Requires<[HasV4T]>;
// Rx=sub(#u8,lsr(Rx,#U5))
def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
- (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
+ (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
"$dst = sub(#$src1, lsr($src2, #$src3))",
[(set (i32 IntRegs:$dst),
(sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
- u8ExtPred:$src1))],
+ u8ImmPred:$src1))],
"$src2 = $dst">,
Requires<[HasV4T]>;
//Shift by immediate and logical.
//Rx=and(#u8,asl(Rx,#U5))
def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
- (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
+ (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
"$dst = and(#$src1, asl($src2, #$src3))",
[(set (i32 IntRegs:$dst),
(and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
- u8ExtPred:$src1))],
+ u8ImmPred:$src1))],
"$src2 = $dst">,
Requires<[HasV4T]>;
//Rx=and(#u8,lsr(Rx,#U5))
def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
- (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
+ (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
"$dst = and(#$src1, lsr($src2, #$src3))",
[(set (i32 IntRegs:$dst),
(and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
- u8ExtPred:$src1))],
+ u8ImmPred:$src1))],
"$src2 = $dst">,
Requires<[HasV4T]>;
//Rx=or(#u8,asl(Rx,#U5))
let AddedComplexity = 30 in
def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
- (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
+ (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
"$dst = or(#$src1, asl($src2, #$src3))",
[(set (i32 IntRegs:$dst),
(or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
- u8ExtPred:$src1))],
+ u8ImmPred:$src1))],
"$src2 = $dst">,
Requires<[HasV4T]>;
//Rx=or(#u8,lsr(Rx,#U5))
let AddedComplexity = 30 in
def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
- (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
+ (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
"$dst = or(#$src1, lsr($src2, #$src3))",
[(set (i32 IntRegs:$dst),
(or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
- u8ExtPred:$src1))],
+ u8ImmPred:$src1))],
"$src2 = $dst">,
Requires<[HasV4T]>;
// memw(Rs+#u6:2) += #U5
let AddedComplexity = 30 in
def MEMw_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
- (ins IntRegs:$base, u6_2Ext:$offset, u5Imm:$addend),
+ (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$addend),
"memw($base+#$offset) += #$addend",
[]>,
Requires<[HasV4T, UseMEMOP]>;
// memw(Rs+#u6:2) -= #U5
let AddedComplexity = 30 in
def MEMw_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
- (ins IntRegs:$base, u6_2Ext:$offset, u5Imm:$subend),
+ (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$subend),
"memw($base+#$offset) -= #$subend",
[]>,
Requires<[HasV4T, UseMEMOP]>;
// memw(Rs+#u6:2) += Rt
let AddedComplexity = 30 in
def MEMw_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
- (ins IntRegs:$base, u6_2Ext:$offset, IntRegs:$addend),
+ (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$addend),
"memw($base+#$offset) += $addend",
- [(store (add (load (add (i32 IntRegs:$base), u6_2ExtPred:$offset)),
+ [(store (add (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
(i32 IntRegs:$addend)),
(add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
Requires<[HasV4T, UseMEMOP]>;
// memw(Rs+#u6:2) -= Rt
let AddedComplexity = 30 in
def MEMw_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
- (ins IntRegs:$base, u6_2Ext:$offset, IntRegs:$subend),
+ (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$subend),
"memw($base+#$offset) -= $subend",
- [(store (sub (load (add (i32 IntRegs:$base), u6_2ExtPred:$offset)),
+ [(store (sub (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
(i32 IntRegs:$subend)),
(add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
Requires<[HasV4T, UseMEMOP]>;
// memw(Rs+#u6:2) &= Rt
let AddedComplexity = 30 in
def MEMw_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
- (ins IntRegs:$base, u6_2Ext:$offset, IntRegs:$andend),
+ (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$andend),
"memw($base+#$offset) &= $andend",
- [(store (and (load (add (i32 IntRegs:$base), u6_2ExtPred:$offset)),
+ [(store (and (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
(i32 IntRegs:$andend)),
(add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
Requires<[HasV4T, UseMEMOP]>;
// memw(Rs+#u6:2) |= Rt
let AddedComplexity = 30 in
def MEMw_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
- (ins IntRegs:$base, u6_2Ext:$offset, IntRegs:$orend),
+ (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$orend),
"memw($base+#$offset) |= $orend",
- [(store (or (load (add (i32 IntRegs:$base), u6_2ExtPred:$offset)),
+ [(store (or (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
(i32 IntRegs:$orend)),
(add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
Requires<[HasV4T, UseMEMOP]>;
// Pd=cmpb.gtu(Rs,#u7)
let isCompare = 1 in
def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
- (ins IntRegs:$src1, u7Ext:$src2),
+ (ins IntRegs:$src1, u7Imm:$src2),
"$dst = cmpb.gtu($src1, #$src2)",
[(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
- u7ExtPred:$src2))]>,
+ u7ImmPred:$src2))]>,
Requires<[HasV4T]>;
// Pd=cmpb.gtu(Rs,Rt)
// Following instruction is not being extended as it results into the incorrect
// code for negative numbers.
-// Following instruction is not being extended as it results into the incorrect
-// code for negative numbers.
-
// Signed half compare(.eq) ri.
// Pd=cmph.eq(Rs,#s8)
let isCompare = 1 in
let isCompare = 1 in
def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
- (ins IntRegs:$src1, s8Ext:$src2),
+ (ins IntRegs:$src1, s8Imm:$src2),
"$dst = cmph.gt($src1, #$src2)",
[(set (i1 PredRegs:$dst),
(setgt (shl (i32 IntRegs:$src1), (i32 16)),
- s8ExtPred:$src2))]>,
+ s8ImmPred:$src2))]>,
Requires<[HasV4T]>;
*/
// Pd=cmph.gtu(Rs,#u7)
let isCompare = 1 in
def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
- (ins IntRegs:$src1, u7Ext:$src2),
+ (ins IntRegs:$src1, u7Imm:$src2),
"$dst = cmph.gtu($src1, #$src2)",
[(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
- u7ExtPred:$src2))]>,
+ u7ImmPred:$src2))]>,
Requires<[HasV4T]>;
//===----------------------------------------------------------------------===//
multiclass ST_abs<string OpcStr> {
let isPredicable = 1 in
def _abs_V4 : STInst2<(outs),
- (ins globaladdressExt:$absaddr, IntRegs:$src),
+ (ins globaladdress:$absaddr, IntRegs:$src),
!strconcat(OpcStr, "(##$absaddr) = $src"),
[]>,
Requires<[HasV4T]>;
let isPredicated = 1 in
def _abs_cPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, globaladdressExt:$absaddr, IntRegs:$src2),
+ (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
!strconcat("if ($src1)",
!strconcat(OpcStr, "(##$absaddr) = $src2")),
[]>,
let isPredicated = 1 in
def _abs_cNotPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, globaladdressExt:$absaddr, IntRegs:$src2),
+ (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
!strconcat("if (!$src1)",
!strconcat(OpcStr, "(##$absaddr) = $src2")),
[]>,
let isPredicated = 1 in
def _abs_cdnPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, globaladdressExt:$absaddr, IntRegs:$src2),
+ (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
!strconcat("if ($src1.new)",
!strconcat(OpcStr, "(##$absaddr) = $src2")),
[]>,
let isPredicated = 1 in
def _abs_cdnNotPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, globaladdressExt:$absaddr, IntRegs:$src2),
+ (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
!strconcat("if (!$src1.new)",
!strconcat(OpcStr, "(##$absaddr) = $src2")),
[]>,
Requires<[HasV4T]>;
def _abs_nv_V4 : STInst2<(outs),
- (ins globaladdressExt:$absaddr, IntRegs:$src),
+ (ins globaladdress:$absaddr, IntRegs:$src),
!strconcat(OpcStr, "(##$absaddr) = $src.new"),
[]>,
Requires<[HasV4T]>;
let isPredicated = 1 in
def _abs_cPt_nv_V4 : STInst2<(outs),
- (ins PredRegs:$src1, globaladdressExt:$absaddr, IntRegs:$src2),
+ (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
!strconcat("if ($src1)",
!strconcat(OpcStr, "(##$absaddr) = $src2.new")),
[]>,
let isPredicated = 1 in
def _abs_cNotPt_nv_V4 : STInst2<(outs),
- (ins PredRegs:$src1, globaladdressExt:$absaddr, IntRegs:$src2),
+ (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
!strconcat("if (!$src1)",
!strconcat(OpcStr, "(##$absaddr) = $src2.new")),
[]>,
let isPredicated = 1 in
def _abs_cdnPt_nv_V4 : STInst2<(outs),
- (ins PredRegs:$src1, globaladdressExt:$absaddr, IntRegs:$src2),
+ (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
!strconcat("if ($src1.new)",
!strconcat(OpcStr, "(##$absaddr) = $src2.new")),
[]>,
let isPredicated = 1 in
def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
- (ins PredRegs:$src1, globaladdressExt:$absaddr, IntRegs:$src2),
+ (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
!strconcat("if (!$src1.new)",
!strconcat(OpcStr, "(##$absaddr) = $src2.new")),
[]>,
let AddedComplexity = 30, isPredicable = 1 in
def STrid_abs_V4 : STInst<(outs),
- (ins globaladdressExt:$absaddr, DoubleRegs:$src),
+ (ins globaladdress:$absaddr, DoubleRegs:$src),
"memd(##$absaddr) = $src",
[(store (i64 DoubleRegs:$src),
(HexagonCONST32 tglobaladdr:$absaddr))]>,
let AddedComplexity = 30, isPredicated = 1 in
def STrid_abs_cPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, globaladdressExt:$absaddr, DoubleRegs:$src2),
+ (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
"if ($src1) memd(##$absaddr) = $src2",
[]>,
Requires<[HasV4T]>;
let AddedComplexity = 30, isPredicated = 1 in
def STrid_abs_cNotPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, globaladdressExt:$absaddr, DoubleRegs:$src2),
+ (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
"if (!$src1) memd(##$absaddr) = $src2",
[]>,
Requires<[HasV4T]>;
let AddedComplexity = 30, isPredicated = 1 in
def STrid_abs_cdnPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, globaladdressExt:$absaddr, DoubleRegs:$src2),
+ (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
"if ($src1.new) memd(##$absaddr) = $src2",
[]>,
Requires<[HasV4T]>;
let AddedComplexity = 30, isPredicated = 1 in
def STrid_abs_cdnNotPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, globaladdressExt:$absaddr, DoubleRegs:$src2),
+ (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
"if (!$src1.new) memd(##$absaddr) = $src2",
[]>,
Requires<[HasV4T]>;
multiclass LD_abs<string OpcStr> {
let isPredicable = 1 in
def _abs_V4 : LDInst2<(outs IntRegs:$dst),
- (ins globaladdressExt:$absaddr),
+ (ins globaladdress:$absaddr),
!strconcat("$dst = ", !strconcat(OpcStr, "(##$absaddr)")),
[]>,
Requires<[HasV4T]>;
let isPredicated = 1 in
def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
- (ins PredRegs:$src1, globaladdressExt:$absaddr),
+ (ins PredRegs:$src1, globaladdress:$absaddr),
!strconcat("if ($src1) $dst = ",
!strconcat(OpcStr, "(##$absaddr)")),
[]>,
let isPredicated = 1 in
def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
- (ins PredRegs:$src1, globaladdressExt:$absaddr),
+ (ins PredRegs:$src1, globaladdress:$absaddr),
!strconcat("if (!$src1) $dst = ",
!strconcat(OpcStr, "(##$absaddr)")),
[]>,
let isPredicated = 1 in
def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
- (ins PredRegs:$src1, globaladdressExt:$absaddr),
+ (ins PredRegs:$src1, globaladdress:$absaddr),
!strconcat("if ($src1.new) $dst = ",
!strconcat(OpcStr, "(##$absaddr)")),
[]>,
let isPredicated = 1 in
def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
- (ins PredRegs:$src1, globaladdressExt:$absaddr),
+ (ins PredRegs:$src1, globaladdress:$absaddr),
!strconcat("if (!$src1.new) $dst = ",
!strconcat(OpcStr, "(##$absaddr)")),
[]>,
let AddedComplexity = 30 in
def LDrid_abs_V4 : LDInst<(outs DoubleRegs:$dst),
- (ins globaladdressExt:$absaddr),
+ (ins globaladdress:$absaddr),
"$dst = memd(##$absaddr)",
[(set (i64 DoubleRegs:$dst),
(load (HexagonCONST32 tglobaladdr:$absaddr)))]>,
let AddedComplexity = 30, isPredicated = 1 in
def LDrid_abs_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
- (ins PredRegs:$src1, globaladdressExt:$absaddr),
+ (ins PredRegs:$src1, globaladdress:$absaddr),
"if ($src1) $dst = memd(##$absaddr)",
[]>,
Requires<[HasV4T]>;
let AddedComplexity = 30, isPredicated = 1 in
def LDrid_abs_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
- (ins PredRegs:$src1, globaladdressExt:$absaddr),
+ (ins PredRegs:$src1, globaladdress:$absaddr),
"if (!$src1) $dst = memd(##$absaddr)",
[]>,
Requires<[HasV4T]>;
let AddedComplexity = 30, isPredicated = 1 in
def LDrid_abs_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
- (ins PredRegs:$src1, globaladdressExt:$absaddr),
+ (ins PredRegs:$src1, globaladdress:$absaddr),
"if ($src1.new) $dst = memd(##$absaddr)",
[]>,
Requires<[HasV4T]>;
let AddedComplexity = 30, isPredicated = 1 in
def LDrid_abs_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
- (ins PredRegs:$src1, globaladdressExt:$absaddr),
+ (ins PredRegs:$src1, globaladdress:$absaddr),
"if (!$src1.new) $dst = memd(##$absaddr)",
[]>,
Requires<[HasV4T]>;
// Transfer global address into a register
let AddedComplexity=50, isMoveImm = 1, isReMaterializable = 1 in
-def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdressExt:$src1),
+def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$src1),
"$dst = ##$src1",
[(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
Requires<[HasV4T]>;
let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
- (ins PredRegs:$src1, globaladdressExt:$src2),
+ (ins PredRegs:$src1, globaladdress:$src2),
"if($src1) $dst = ##$src2",
[]>,
Requires<[HasV4T]>;
let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
- (ins PredRegs:$src1, globaladdressExt:$src2),
+ (ins PredRegs:$src1, globaladdress:$src2),
"if(!$src1) $dst = ##$src2",
[]>,
Requires<[HasV4T]>;
let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
- (ins PredRegs:$src1, globaladdressExt:$src2),
+ (ins PredRegs:$src1, globaladdress:$src2),
"if($src1.new) $dst = ##$src2",
[]>,
Requires<[HasV4T]>;
let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
- (ins PredRegs:$src1, globaladdressExt:$src2),
+ (ins PredRegs:$src1, globaladdress:$src2),
"if(!$src1.new) $dst = ##$src2",
[]>,
Requires<[HasV4T]>;
// as an operand
let AddedComplexity = 10 in
def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
- (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
+ (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
"$dst=memd($src1<<#$src2+##$offset)",
[(set (i64 DoubleRegs:$dst),
(load (add (shl IntRegs:$src1, u2ImmPred:$src2),
let AddedComplexity = 10 in
multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
def _lo_V4 : LDInst<(outs IntRegs:$dst),
- (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
+ (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
!strconcat("$dst = ",
!strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
[(set IntRegs:$dst,
// as an operand
let AddedComplexity = 10 in
def STrid_ind_lo_V4 : STInst<(outs),
- (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$src3,
+ (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
DoubleRegs:$src4),
"memd($src1<<#$src2+#$src3) = $src4",
[(store (i64 DoubleRegs:$src4),
let AddedComplexity = 10 in
multiclass ST_indirect_lo<string OpcStr, PatFrag OpNode> {
def _lo_V4 : STInst<(outs),
- (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$src3,
+ (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
IntRegs:$src4),
!strconcat(OpcStr, "($src1<<#$src2+##$src3) = $src4"),
[(OpNode (i32 IntRegs:$src4),
multiclass ST_absimm<string OpcStr> {
let isPredicable = 1 in
def _abs_V4 : STInst2<(outs),
- (ins u6Ext:$src1, IntRegs:$src2),
+ (ins u6Imm:$src1, IntRegs:$src2),
!strconcat(OpcStr, "(#$src1) = $src2"),
[]>,
Requires<[HasV4T]>;
let isPredicated = 1 in
def _abs_cPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, u6Ext:$src2, IntRegs:$src3),
+ (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
!strconcat("if ($src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
[]>,
Requires<[HasV4T]>;
let isPredicated = 1 in
def _abs_cNotPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, u6Ext:$src2, IntRegs:$src3),
+ (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
!strconcat("if (!$src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
[]>,
Requires<[HasV4T]>;
let isPredicated = 1 in
def _abs_cdnPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, u6Ext:$src2, IntRegs:$src3),
+ (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
!strconcat("if ($src1.new)",
!strconcat(OpcStr, "(#$src2) = $src3")),
[]>,
let isPredicated = 1 in
def _abs_cdnNotPt_V4 : STInst2<(outs),
- (ins PredRegs:$src1, u6Ext:$src2, IntRegs:$src3),
+ (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
!strconcat("if (!$src1.new)",
!strconcat(OpcStr, "(#$src2) = $src3")),
[]>,
Requires<[HasV4T]>;
def _abs_nv_V4 : STInst2<(outs),
- (ins u6Ext:$src1, IntRegs:$src2),
+ (ins u6Imm:$src1, IntRegs:$src2),
!strconcat(OpcStr, "(#$src1) = $src2.new"),
[]>,
Requires<[HasV4T]>;
let isPredicated = 1 in
def _abs_cPt_nv_V4 : STInst2<(outs),
- (ins PredRegs:$src1, u6Ext:$src2, IntRegs:$src3),
+ (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
!strconcat("if ($src1)",
!strconcat(OpcStr, "(#$src2) = $src3.new")),
[]>,
let isPredicated = 1 in
def _abs_cNotPt_nv_V4 : STInst2<(outs),
- (ins PredRegs:$src1, u6Ext:$src2, IntRegs:$src3),
+ (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
!strconcat("if (!$src1)",
!strconcat(OpcStr, "(#$src2) = $src3.new")),
[]>,
let isPredicated = 1 in
def _abs_cdnPt_nv_V4 : STInst2<(outs),
- (ins PredRegs:$src1, u6Ext:$src2, IntRegs:$src3),
+ (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
!strconcat("if ($src1.new)",
!strconcat(OpcStr, "(#$src2) = $src3.new")),
[]>,
let isPredicated = 1 in
def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
- (ins PredRegs:$src1, u6Ext:$src2, IntRegs:$src3),
+ (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
!strconcat("if (!$src1.new)",
!strconcat(OpcStr, "(#$src2) = $src3.new")),
[]>,
defm STriw_imm : ST_absimm<"memw">;
let Predicates = [HasV4T], AddedComplexity = 30 in
-def : Pat<(truncstorei8 (i32 IntRegs:$src1), u6ExtPred:$src2),
- (STrib_imm_abs_V4 u6ExtPred:$src2, IntRegs: $src1)>;
+def : Pat<(truncstorei8 (i32 IntRegs:$src1), u6ImmPred:$src2),
+ (STrib_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
let Predicates = [HasV4T], AddedComplexity = 30 in
-def : Pat<(truncstorei16 (i32 IntRegs:$src1), u6ExtPred:$src2),
- (STrih_imm_abs_V4 u6ExtPred:$src2, IntRegs: $src1)>;
+def : Pat<(truncstorei16 (i32 IntRegs:$src1), u6ImmPred:$src2),
+ (STrih_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
let Predicates = [HasV4T], AddedComplexity = 30 in
-def : Pat<(store (i32 IntRegs:$src1), u6ExtPred:$src2),
- (STriw_imm_abs_V4 u6ExtPred:$src2, IntRegs: $src1)>;
+def : Pat<(store (i32 IntRegs:$src1), u6ImmPred:$src2),
+ (STriw_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
// Load - absolute addressing mode: These instruction take constant
multiclass LD_absimm<string OpcStr> {
let isPredicable = 1 in
def _abs_V4 : LDInst2<(outs IntRegs:$dst),
- (ins u6Ext:$src),
+ (ins u6Imm:$src),
!strconcat("$dst = ",
!strconcat(OpcStr, "(#$src)")),
[]>,
let isPredicated = 1 in
def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
- (ins PredRegs:$src1, u6Ext:$src2),
+ (ins PredRegs:$src1, u6Imm:$src2),
!strconcat("if ($src1) $dst = ",
!strconcat(OpcStr, "(#$src2)")),
[]>,
let isPredicated = 1 in
def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
- (ins PredRegs:$src1, u6Ext:$src2),
+ (ins PredRegs:$src1, u6Imm:$src2),
!strconcat("if (!$src1) $dst = ",
!strconcat(OpcStr, "(#$src2)")),
[]>,
let isPredicated = 1 in
def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
- (ins PredRegs:$src1, u6Ext:$src2),
+ (ins PredRegs:$src1, u6Imm:$src2),
!strconcat("if ($src1.new) $dst = ",
!strconcat(OpcStr, "(#$src2)")),
[]>,
let isPredicated = 1 in
def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
- (ins PredRegs:$src1, u6Ext:$src2),
+ (ins PredRegs:$src1, u6Imm:$src2),
!strconcat("if (!$src1.new) $dst = ",
!strconcat(OpcStr, "(#$src2)")),
[]>,
defm LDriw_imm : LD_absimm<"memw">;
let Predicates = [HasV4T], AddedComplexity = 30 in
-def : Pat<(i32 (load u6ExtPred:$src)),
- (LDriw_imm_abs_V4 u6ExtPred:$src)>;
+def : Pat<(i32 (load u6ImmPred:$src)),
+ (LDriw_imm_abs_V4 u6ImmPred:$src)>;
let Predicates = [HasV4T], AddedComplexity=30 in
-def : Pat<(i32 (sextloadi8 u6ExtPred:$src)),
- (LDrib_imm_abs_V4 u6ExtPred:$src)>;
+def : Pat<(i32 (sextloadi8 u6ImmPred:$src)),
+ (LDrib_imm_abs_V4 u6ImmPred:$src)>;
let Predicates = [HasV4T], AddedComplexity=30 in
-def : Pat<(i32 (zextloadi8 u6ExtPred:$src)),
- (LDriub_imm_abs_V4 u6ExtPred:$src)>;
+def : Pat<(i32 (zextloadi8 u6ImmPred:$src)),
+ (LDriub_imm_abs_V4 u6ImmPred:$src)>;
let Predicates = [HasV4T], AddedComplexity=30 in
-def : Pat<(i32 (sextloadi16 u6ExtPred:$src)),
- (LDrih_imm_abs_V4 u6ExtPred:$src)>;
+def : Pat<(i32 (sextloadi16 u6ImmPred:$src)),
+ (LDrih_imm_abs_V4 u6ImmPred:$src)>;
let Predicates = [HasV4T], AddedComplexity=30 in
-def : Pat<(i32 (zextloadi16 u6ExtPred:$src)),
- (LDriuh_imm_abs_V4 u6ExtPred:$src)>;
+def : Pat<(i32 (zextloadi16 u6ImmPred:$src)),
+ (LDriuh_imm_abs_V4 u6ImmPred:$src)>;
// Indexed store double word - global address.
// memw(Rs+#u6:2)=#S8
let AddedComplexity = 10 in
def STriw_offset_ext_V4 : STInst<(outs),
- (ins IntRegs:$src1, u6_2Imm:$src2, globaladdressExt:$src3),
+ (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
"memw($src1+#$src2) = ##$src3",
[(store (HexagonCONST32 tglobaladdr:$src3),
(add IntRegs:$src1, u6_2ImmPred:$src2))]>,
// memw(Rs+#u6:2)=#S8
let AddedComplexity = 10 in
def STrih_offset_ext_V4 : STInst<(outs),
- (ins IntRegs:$src1, u6_1Imm:$src2, globaladdressExt:$src3),
+ (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
"memh($src1+#$src2) = ##$src3",
[(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
(add IntRegs:$src1, u6_1ImmPred:$src2))]>,
projects / oota-llvm.git / commitdiff