Next step in Mips16 prologue/epilogue cleanup.

Save S2(reg 18) only when we are calling floating point stubs that
have a return value of float or complex. Some more work to make this
better but this is the first step.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196921 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/Mips16FrameLowering.cpp b/lib/Target/Mips/Mips16FrameLowering.cpp
index 6655ff98e033f5f5b374ba5b65be5ead86a2cc87..ae6be05cdfbb07ee95aced7aee84b6e26329a6bb 100644 (file)
--- a/lib/Target/Mips/Mips16FrameLowering.cpp
+++ b/lib/Target/Mips/Mips16FrameLowering.cpp
@@ -15,6 +15,7 @@
 #include "MCTargetDesc/MipsBaseInfo.h"
 #include "Mips16InstrInfo.h"
 #include "MipsInstrInfo.h"
+#include "MipsRegisterInfo.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -56,17 +57,31 @@ void Mips16FrameLowering::emitPrologue(MachineFunction &MF) const {
   MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol();
   BuildMI(MBB, MBBI, dl,
           TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
-  unsigned S2 = MRI->getDwarfRegNum(Mips::S2, true);
-  MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, S2, -8));
+
+
+  const MipsRegisterInfo &RI = TII.getRegisterInfo();
+  const BitVector Reserved = RI.getReservedRegs(MF);
+  bool SaveS2 = Reserved[Mips::S2];
+  int Offset=-4;
+  unsigned RA = MRI->getDwarfRegNum(Mips::RA, true);
+  MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, RA, Offset));
+  Offset -= 4;
+
+  if (SaveS2) {
+    unsigned S2 = MRI->getDwarfRegNum(Mips::S2, true);
+    MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, S2, Offset));
+    Offset -= 4;
+  }
+
 
   unsigned S1 = MRI->getDwarfRegNum(Mips::S1, true);
-  MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, S1, -12));
+  MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, S1, Offset));
+  Offset -= 4;
 
   unsigned S0 = MRI->getDwarfRegNum(Mips::S0, true);
-  MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, S0, -16));
+  MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, S0, Offset));
+
 
-  unsigned RA = MRI->getDwarfRegNum(Mips::RA, true);
-  MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, RA, -4));
 
   if (hasFP(MF))
     BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)

diff --git a/lib/Target/Mips/Mips16HardFloat.cpp b/lib/Target/Mips/Mips16HardFloat.cpp
index 81bf18cd09d93566aeb2db949fa6b1947fa4854b..65dbd74a1c8a4524c65b3a33159e1bb002d010c4 100644 (file)
--- a/lib/Target/Mips/Mips16HardFloat.cpp
+++ b/lib/Target/Mips/Mips16HardFloat.cpp
@@ -400,13 +400,19 @@ static bool fixupFPReturnAndCall
         Value *F = (M->getOrInsertFunction(Name, A, MyVoid, T, NULL));
         CallInst::Create(F, Params, "", &Inst );
       } else if (const CallInst *CI = dyn_cast<CallInst>(I)) {
+          Function *F_ =  CI->getCalledFunction();
+          if (F_ && !isIntrinsicInline(F_)) {
           // pic mode calls are handled by already defined
           // helper functions
-          if (Subtarget.getRelocationModel() != Reloc::PIC_ ) {
-            Function *F_ =  CI->getCalledFunction();
-            if (F_ && !isIntrinsicInline(F_) && needsFPHelperFromSig(*F_)) {
-              assureFPCallStub(*F_, M, Subtarget);
+            if (needsFPReturnHelper(*F_)) {
               Modified=true;
+              F.addFnAttr("saveS2");
+            }
+            if (Subtarget.getRelocationModel() != Reloc::PIC_ ) {
+              if (needsFPHelperFromSig(*F_)) {
+                assureFPCallStub(*F_, M, Subtarget);
+                Modified=true;
+              }
             }
           }
       }

diff --git a/lib/Target/Mips/Mips16InstrInfo.cpp b/lib/Target/Mips/Mips16InstrInfo.cpp
index 3736358bb6d91015f28a6b45006ca6b0808f62dd..2df83e8850685a8d7e32462ab096f5dbb609cff9 100644 (file)
--- a/lib/Target/Mips/Mips16InstrInfo.cpp
+++ b/lib/Target/Mips/Mips16InstrInfo.cpp
@@ -173,22 +173,29 @@ void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
                     MachineBasicBlock &MBB,
                     MachineBasicBlock::iterator I) const {
   DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
+  const BitVector Reserved = RI.getReservedRegs(*MBB.getParent());
+  bool SaveS2 = Reserved[Mips::S2];
+  MachineInstrBuilder MIB;
   if (isUInt<11>(FrameSize))
-    BuildMI(MBB, I, DL, get(Mips::SaveX16)).addReg(Mips::RA).
+    MIB = BuildMI(
+            MBB, I, DL, get(Mips::SaveX16)).addReg(Mips::RA).
             addReg(Mips::S0).
-            addReg(Mips::S1).addReg(Mips::S2).addImm(FrameSize);
+            addReg(Mips::S1).addImm(FrameSize);
   else {
     int Base = 2040; // should create template function like isUInt that
                      // returns largest possible n bit unsigned integer
     int64_t Remainder = FrameSize - Base;
-    BuildMI(MBB, I, DL, get(Mips::SaveX16)).addReg(Mips::RA).
+    MIB = BuildMI(
+            MBB, I, DL, get(Mips::SaveX16)).addReg(Mips::RA).
             addReg(Mips::S0).
-            addReg(Mips::S1).addReg(Mips::S2).addImm(Base);
+            addReg(Mips::S1).addImm(Base);
     if (isInt<16>(-Remainder))
       BuildAddiuSpImm(MBB, I, -Remainder);
     else
       adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
   }
+  if (SaveS2)
+    MIB.addReg(Mips::S2);
 }
 
 // Adjust SP by FrameSize bytes. Restore RA, S0, S1
@@ -196,12 +203,16 @@ void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
                                    MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator I) const {
   DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
+  const BitVector Reserved = RI.getReservedRegs(*MBB.getParent());
+  bool SaveS2 = Reserved[Mips::S2];
+  MachineInstrBuilder MIB;
   if (isUInt<11>(FrameSize))
-    BuildMI(MBB, I, DL, get(Mips::RestoreX16)).
+    MIB = BuildMI(
+            MBB, I, DL, get(Mips::RestoreX16)).
             addReg(Mips::RA, RegState::Define).
             addReg(Mips::S0, RegState::Define).
             addReg(Mips::S1, RegState::Define).
-            addReg(Mips::S2, RegState::Define).addImm(FrameSize);
+            addImm(FrameSize);
   else {
     int Base = 2040; // should create template function like isUInt that
                      // returns largest possible n bit unsigned integer
@@ -210,12 +221,15 @@ void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
       BuildAddiuSpImm(MBB, I, Remainder);
     else
       adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
-    BuildMI(MBB, I, DL, get(Mips::RestoreX16)).
+    MIB = BuildMI(
+            MBB, I, DL, get(Mips::RestoreX16)).
             addReg(Mips::RA, RegState::Define).
             addReg(Mips::S0, RegState::Define).
             addReg(Mips::S1, RegState::Define).
-            addReg(Mips::S2, RegState::Define).addImm(Base);
+            addImm(Base);
   }
+  if (SaveS2)
+    MIB.addReg(Mips::S2, RegState::Define);
 }
 
 // Adjust SP by Amount bytes where bytes can be up to 32bit number.

diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp
index 3105b0208451ec16a034745c7d1fd4b98af620c3..65b1f8cf2d1096ee4c2176be6be1b7e53a9e224f 100644 (file)
--- a/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -27,6 +27,7 @@
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/DebugInfo.h"
 #include "llvm/IR/Constants.h"
+#include "llvm/IR/Function.h"
 #include "llvm/IR/Type.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
@@ -183,6 +184,8 @@ getReservedRegs(const MachineFunction &MF) const {
     Reserved.set(Mips::RA_64);
     Reserved.set(Mips::T0);
     Reserved.set(Mips::T1);
+    if (MF.getFunction()->hasFnAttribute("saveS2"))
+      Reserved.set(Mips::S2);
   }
 
   // Reserve GP if small section is used.

diff --git a/test/CodeGen/Mips/align16.ll b/test/CodeGen/Mips/align16.ll
index 1b724e9fc86a809cc459860bb643807b4e58ade0..32ec94bd20c12c850f7d4adba13beaef095cbef0 100644 (file)
--- a/test/CodeGen/Mips/align16.ll
+++ b/test/CodeGen/Mips/align16.ll
@@ -25,7 +25,7 @@ entry:
   call void @p(i32* %arrayidx1)
   ret void
 }
-; 16:  save    $ra, $16, $17, $18, 2040
+; 16:  save    $ra, $16, $17, 2040
 ; 16:  addiu   $sp, -56 # 16 bit inst
 ; 16:  addiu   $sp, 56 # 16 bit inst
-; 16:  restore $ra,  $16, $17, $18, 2040
+; 16:  restore $ra,  $16, $17, 2040

diff --git a/test/CodeGen/Mips/alloca16.ll b/test/CodeGen/Mips/alloca16.ll
index a836d1248897d61655b062af299d95523275ed0e..5bdf4dd7835b0acd43363658181b5114d46b5c08 100644 (file)
--- a/test/CodeGen/Mips/alloca16.ll
+++ b/test/CodeGen/Mips/alloca16.ll
@@ -20,7 +20,7 @@ entry:
 define void @test() nounwind {
 entry:
 ; 16:  .frame  $sp,24,$ra
-; 16:  save    $ra, $16, $17, $18, 24
+; 16:  save    $ra, $16, $17, 24
 ; 16:  move    $16, $sp
 ; 16:  move    ${{[0-9]+}}, $sp
 ; 16:  subu    $[[REGISTER:[0-9]+]], ${{[0-9]+}}, ${{[0-9]+}}

diff --git a/test/CodeGen/Mips/ex2.ll b/test/CodeGen/Mips/ex2.ll
index 5b3463e509497e386ad5c92c8218b173f6aa617a..75562156cf0e79ba52fc76600849095623455992 100644 (file)
--- a/test/CodeGen/Mips/ex2.ll
+++ b/test/CodeGen/Mips/ex2.ll
@@ -6,12 +6,11 @@
 define i32 @main() {
 ; 16-LABEL: main:
 ; 16:  .cfi_startproc
-; 16:  save    $ra, $16, $17, $18, 40
+; 16:  save    $ra, $16, $17, 40
 ; 16:   .cfi_def_cfa_offset 40
-; 16:   .cfi_offset 18, -8
-; 16:   .cfi_offset 17, -12
-; 16:  .cfi_offset 16, -16
 ; 16:  .cfi_offset 31, -4
+; 16:   .cfi_offset 17, -8
+; 16:  .cfi_offset 16, -12
 ; 16:   .cfi_endproc
 entry:
   %retval = alloca i32, align 4

diff --git a/test/CodeGen/Mips/helloworld.ll b/test/CodeGen/Mips/helloworld.ll
index 32bc45fba38fc080d1b7558cfdfdbf9b5e321fee..d363006a550481baccb5199de48f0d996922f4dd 100644 (file)
--- a/test/CodeGen/Mips/helloworld.ll
+++ b/test/CodeGen/Mips/helloworld.ll
@@ -25,7 +25,7 @@ entry:
 ; SR32:  .set noreorder
 ; SR32:  .set nomacro
 ; SR32:  .set noat
-; SR:  save    $ra, $16, $17, $18, [[FS:[0-9]+]]
+; SR:  save    $ra, $16, $17, [[FS:[0-9]+]]
 ; PE:    .ent main
 ; PE:    .align  2
 ; PE-NEXT:     li      $[[T1:[0-9]+]], %hi(_gp_disp)
@@ -37,7 +37,7 @@ entry:
 ; C2:  move    $25, ${{[0-9]+}}
 ; C1:  move    $gp, ${{[0-9]+}}
 ; C1:  jalrc   ${{[0-9]+}}
-; SR:  restore         $ra, $16, $17, $18, [[FS]]
+; SR:  restore         $ra, $16, $17, [[FS]]
 ; PE:  li      $2, 0
 ; PE:  jrc     $ra
 

diff --git a/test/CodeGen/Mips/s2rem.ll b/test/CodeGen/Mips/s2rem.ll
new file mode 100644 (file)
index 0000000..0f0b3ed
--- /dev/null
+++ b/test/CodeGen/Mips/s2rem.ll
@@ -0,0 +1,95 @@
+; RUN: llc  -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic  < %s | FileCheck %s -check-prefix=NEG
+
+; RUN: llc  -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static  < %s | FileCheck %s -check-prefix=NEG
+
+; RUN: llc  -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic  < %s | FileCheck %s 
+
+; RUN: llc  -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static  < %s | FileCheck %s 
+
+@xi = common global i32 0, align 4
+@x = common global float 0.000000e+00, align 4
+@xd = common global double 0.000000e+00, align 8
+
+; Function Attrs: nounwind
+define void @it() #0 {
+entry:
+  %call = call i32 @i(i32 1)
+  store i32 %call, i32* @xi, align 4
+  ret void
+; CHECK:       .ent    it
+; NEG:         .ent    it
+; CHECK:       save    $ra, $16, $17, [[FS:[0-9]+]]
+; NEG-NOT:      save   $ra, $16, $17, [[FS:[0-9]+]], $18
+; CHECK:       restore $ra, $16, $17, [[FS]]
+; NEG-NOT:      restore        $ra, $16, $17, [[FS:[0-9]+]], $18
+; CHECK:       .end    it
+; NEG:         .end    it
+}
+
+declare i32 @i(i32) #1
+
+; Function Attrs: nounwind
+define void @ft() #0 {
+entry:
+  %call = call float @f()
+  store float %call, float* @x, align 4
+  ret void
+; CHECK:       .ent    ft
+; CHECK:       save    $ra, $16, $17, [[FS:[0-9]+]], $18
+; CHECK:       restore $ra, $16, $17, [[FS]], $18
+; CHECK:       .end    ft
+}
+
+declare float @f() #1
+
+; Function Attrs: nounwind
+define void @dt() #0 {
+entry:
+  %call = call double @d()
+  store double %call, double* @xd, align 8
+  ret void
+; CHECK:       .ent    dt
+; CHECK:       save    $ra, $16, $17, [[FS:[0-9]+]], $18
+; CHECK:       restore $ra, $16, $17, [[FS]], $18
+; CHECK:       .end    dt
+}
+
+declare double @d() #1
+
+; Function Attrs: nounwind
+define void @fft() #0 {
+entry:
+  %0 = load float* @x, align 4
+  %call = call float @ff(float %0)
+  store float %call, float* @x, align 4
+  ret void
+; CHECK:       .ent    fft
+; CHECK:       save    $ra, $16, $17, [[FS:[0-9]+]], $18
+; CHECK:       restore $ra, $16, $17, [[FS]], $18
+; CHECK:       .end    fft
+}
+
+declare float @ff(float) #1
+
+; Function Attrs: nounwind
+define void @vft() #0 {
+entry:
+  %0 = load float* @x, align 4
+  call void @vf(float %0)
+  ret void
+; CHECK:       .ent    vft
+; NEG:         .ent    vft
+; CHECK:       save    $ra, $16, $17, [[FS:[0-9]+]]
+; NEG-NOT:      save   $ra, $16, $17, [[FS:[0-9]+]], $18
+; CHECK:       restore $ra, $16, $17, [[FS]]
+; NEG-NOT:      restore        $ra, $16, $17, [[FS:[0-9]+]], $18
+; CHECK:       .end    vft
+; NEG:         .end    vft
+}
+
+declare void @vf(float) #1
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+