#define RK30_CRU_BASE RK2928_CRU_BASE
#define RK30_GRF_BASE RK2928_GRF_BASE
#define RK30_IMEM_BASE RK2928_IMEM_BASE
+#define RK30_IMEM_NONCACHED RK2928_IMEM_NONCACHED
#define RK30_PTIMER_BASE RK2928_PTIMER_BASE
#define RK30_ROM_BASE RK2928_ROM_BASE
#define RK30_SCU_BASE RK2928_SCU_BASE
for (i = 1; i < ncores; i++)
pmu_set_power_domain(PD_A9_0 + i, false);
- memcpy(RK30_IMEM_BASE, rk30_sram_secondary_startup, sz);
- flush_icache_range((unsigned long)RK30_IMEM_BASE, (unsigned long)RK30_IMEM_BASE + sz);
- outer_clean_range(0, sz);
+ memcpy(RK30_IMEM_NONCACHED, rk30_sram_secondary_startup, sz);
+ isb();
+ dsb();
first = false;
}
- dsb_sev();
pmu_set_power_domain(PD_A9_0 + cpu, true);
return 0;