Don't add or sub zero to sp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33142 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 4890e3094fe6e0af0111ef7bf00a6ca0127d4806..16a1a29660e2bc05723c83970c5c9257948237d0 100644 (file)
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -206,9 +206,11 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
 
   MFI->setStackSize(NumBytes);
 
-  //sub sp, sp, #NumBytes
-  splitInstructionWithImmediate(MBB, MBBI, TII.get(ARM::SUB), ARM::R13,
-                            ARM::R13, NumBytes);
+  if (NumBytes) {
+    //sub sp, sp, #NumBytes
+    splitInstructionWithImmediate(MBB, MBBI, TII.get(ARM::SUB), ARM::R13,
+                                  ARM::R13, NumBytes);
+  }
 
 
   if (HasFP) {
@@ -234,9 +236,11 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
     BuildMI(MBB, MBBI, TII.get(ARM::LDR), ARM::R11).addReg(ARM::R13).addImm(0);
   }
 
-  //add sp, sp, #NumBytes
-  splitInstructionWithImmediate(MBB, MBBI, TII.get(ARM::ADD), ARM::R13,
-                            ARM::R13, NumBytes);
+  if (NumBytes){
+    //add sp, sp, #NumBytes
+    splitInstructionWithImmediate(MBB, MBBI, TII.get(ARM::ADD), ARM::R13,
+                                  ARM::R13, NumBytes);
+  }
 
 }
 

diff --git a/test/CodeGen/ARM/spaddsub.ll b/test/CodeGen/ARM/spaddsub.ll
new file mode 100644 (file)
index 0000000..ef3b9b7
--- /dev/null
+++ b/test/CodeGen/ARM/spaddsub.ll
@@ -0,0 +1,10 @@
+; RUN: llvm-upgrade < %s | llvm-as | llc -f -march=arm -o %t.s &&
+; RUN: not grep "add r13, r13, #0" < %t.s &&
+; RUN: not grep "sub r13, r13, #0" < %t.s
+
+int %f() {
+entry:
+       ret int 1
+}
+
+