rk: move rk29-ipp.h from mach-rk29 to plat-rk

diff --git a/arch/arm/mach-rk29/include/mach/rk29-ipp.h b/arch/arm/mach-rk29/include/mach/rk29-ipp.h
deleted file mode 100755 (executable)
index 488f6e8..0000000
--- a/arch/arm/mach-rk29/include/mach/rk29-ipp.h
+++ /dev/null
@@ -1,132 +0,0 @@
-#ifndef _RK29_IPP_DRIVER_H_\r
-#define _RK29_IPP_DRIVER_H_\r
-\r
-\r
-#define IPP_BLIT_SYNC  0x5017\r
-#define IPP_BLIT_ASYNC  0x5018\r
-#define IPP_GET_RESULT  0x5019\r
-\r
-\r
-/* Image data */\r
-struct rk29_ipp_image\r
-{\r
-       uint32_t        YrgbMst;        // image Y/rgb address\r
-       uint32_t    CbrMst;     // image CbCr address\r
-       uint32_t        w;      // image full width\r
-       uint32_t        h;      // image full height\r
-       uint32_t        fmt;    // color format\r
-};\r
-\r
-struct rk29_ipp_req {\r
-       struct rk29_ipp_image src0; // source0 image\r
-       struct rk29_ipp_image dst0; // destination0 image\r
-       //struct rk29_ipp_image src1; // source1 image\r
-       //struct rk29_ipp_image dst1; // destination1 image\r
-       uint32_t src_vir_w;\r
-       uint32_t dst_vir_w;\r
-       uint32_t timeout;\r
-       \r
-       uint32_t flag; //rotate\r
-\r
-       /*store_clip_mode \r
-           0:when src width is not 64-bits aligned,use dummy data make it 64-bits aligned  1:packed\r
-          we usually set to 0\r
-       */\r
-       uint8_t store_clip_mode;\r
-       \r
-       //deinterlace_enable  0:disable 1:enable 2:query\r
-       uint8_t deinterlace_enable;\r
-       //the sum of three paras should be 32,and single para should be less than 32\r
-       uint8_t deinterlace_para0;\r
-       uint8_t deinterlace_para1;\r
-       uint8_t deinterlace_para2;\r
-       \r
-       /* completion is reported through a callback */\r
-       void                    (*complete)(int retval);\r
-               \r
-};\r
-\r
-//format enum\r
-enum\r
-{\r
-       IPP_XRGB_8888 = 0,\r
-       IPP_RGB_565 =1 ,\r
-       IPP_Y_CBCR_H2V1 = 2,  //yuv 422sp\r
-       IPP_Y_CBCR_H2V2 = 3, //yuv 420sp\r
-       IPP_Y_CBCR_H1V1 =6, //yuv 444sp\r
-       IPP_IMGTYPE_LIMIT\r
-};\r
-\r
-typedef enum\r
- {\r
-     IPP_ROT_90,\r
-     IPP_ROT_180,\r
-     IPP_ROT_270,\r
-     IPP_ROT_X_FLIP,\r
-     IPP_ROT_Y_FLIP,\r
-     IPP_ROT_0,\r
-     IPP_ROT_LIMIT\r
- } ROT_DEG;\r
-\r
- struct ipp_regs {\r
-       uint32_t ipp_config;\r
-       uint32_t ipp_src_img_info;\r
-       uint32_t ipp_dst_img_info;\r
-       uint32_t ipp_img_vir;\r
-       uint32_t ipp_int;\r
-       uint32_t ipp_src0_y_mst;\r
-       uint32_t ipp_src0_Cbr_mst;\r
-       uint32_t ipp_src1_y_mst;\r
-       uint32_t ipp_src1_Cbr_mst;\r
-       uint32_t ipp_dst0_y_mst;\r
-       uint32_t ipp_dst0_Cbr_mst;\r
-       uint32_t ipp_dst1_y_mst;\r
-       uint32_t ipp_dst1_Cbr_mst;\r
-       uint32_t ipp_pre_scl_para;\r
-       uint32_t ipp_post_scl_para;\r
-       uint32_t ipp_swap_ctrl;\r
-       uint32_t ipp_pre_img_info;\r
-       uint32_t ipp_axi_id;\r
-       uint32_t ipp_process_st;\r
-};\r
-\r
-#define IPP_CONFIG                             (0x00)\r
-#define IPP_SRC_IMG_INFO               (0x04)\r
-#define IPP_DST_IMG_INFO               (0x08)\r
-#define IPP_IMG_VIR                            (0x0c)\r
-#define IPP_INT                                        (0x10)\r
-#define IPP_SRC0_Y_MST                 (0x14)\r
-#define IPP_SRC0_CBR_MST               (0x18)\r
-#define IPP_SRC1_Y_MST                 (0x1c)\r
-#define IPP_SRC1_CBR_MST               (0x20)\r
-#define IPP_DST0_Y_MST                 (0x24)\r
-#define IPP_DST0_CBR_MST               (0x28)\r
-#define IPP_DST1_Y_MST                 (0x2c)\r
-#define IPP_DST1_CBR_MST               (0x30)\r
-#define IPP_PRE_SCL_PARA               (0x34)\r
-#define IPP_POST_SCL_PARA              (0x38)\r
-#define IPP_SWAP_CTRL                  (0x3c)\r
-#define IPP_PRE_IMG_INFO               (0x40)\r
-#define IPP_AXI_ID                             (0x44)\r
-#define IPP_SRESET                             (0x48)\r
-#define IPP_PROCESS_ST                 (0x50)\r
-\r
-/*ipp config*/\r
-#define STORE_CLIP_MODE                        (1<<26)\r
-#define DEINTERLACE_ENABLE             (1<<24)\r
-#define ROT_ENABLE                             (1<<8)\r
-#define PRE_SCALE                              (1<<4)\r
-#define POST_SCALE                             (1<<3)\r
-\r
-#define IPP_BLIT_COMPLETE_EVENT BIT(1)\r
-\r
-#define IS_YCRCB(img) ((img == IPP_Y_CBCR_H2V1) | (img == IPP_Y_CBCR_H2V2) | \\r
-                      (img == IPP_Y_CBCR_H1V1) )\r
-#define IS_RGB(img) ((img == IPP_RGB_565) | (img == IPP_ARGB_8888) | \\r
-                    (img == IPP_XRGB_8888) ))\r
-#define HAS_ALPHA(img) (img == IPP_ARGB_8888)\r
-\r
-\r
-int ipp_blit_async(const struct rk29_ipp_req *req);\r
-int ipp_blit_sync(const struct rk29_ipp_req *req);\r
-#endif /*_RK29_IPP_DRIVER_H_*/
\ No newline at end of file

diff --git a/arch/arm/plat-rk/include/plat/ipp.h b/arch/arm/plat-rk/include/plat/ipp.h
new file mode 100755 (executable)
index 0000000..488f6e8
--- /dev/null
+++ b/arch/arm/plat-rk/include/plat/ipp.h
@@ -0,0 +1,132 @@
+#ifndef _RK29_IPP_DRIVER_H_\r
+#define _RK29_IPP_DRIVER_H_\r
+\r
+\r
+#define IPP_BLIT_SYNC  0x5017\r
+#define IPP_BLIT_ASYNC  0x5018\r
+#define IPP_GET_RESULT  0x5019\r
+\r
+\r
+/* Image data */\r
+struct rk29_ipp_image\r
+{\r
+       uint32_t        YrgbMst;        // image Y/rgb address\r
+       uint32_t    CbrMst;     // image CbCr address\r
+       uint32_t        w;      // image full width\r
+       uint32_t        h;      // image full height\r
+       uint32_t        fmt;    // color format\r
+};\r
+\r
+struct rk29_ipp_req {\r
+       struct rk29_ipp_image src0; // source0 image\r
+       struct rk29_ipp_image dst0; // destination0 image\r
+       //struct rk29_ipp_image src1; // source1 image\r
+       //struct rk29_ipp_image dst1; // destination1 image\r
+       uint32_t src_vir_w;\r
+       uint32_t dst_vir_w;\r
+       uint32_t timeout;\r
+       \r
+       uint32_t flag; //rotate\r
+\r
+       /*store_clip_mode \r
+           0:when src width is not 64-bits aligned,use dummy data make it 64-bits aligned  1:packed\r
+          we usually set to 0\r
+       */\r
+       uint8_t store_clip_mode;\r
+       \r
+       //deinterlace_enable  0:disable 1:enable 2:query\r
+       uint8_t deinterlace_enable;\r
+       //the sum of three paras should be 32,and single para should be less than 32\r
+       uint8_t deinterlace_para0;\r
+       uint8_t deinterlace_para1;\r
+       uint8_t deinterlace_para2;\r
+       \r
+       /* completion is reported through a callback */\r
+       void                    (*complete)(int retval);\r
+               \r
+};\r
+\r
+//format enum\r
+enum\r
+{\r
+       IPP_XRGB_8888 = 0,\r
+       IPP_RGB_565 =1 ,\r
+       IPP_Y_CBCR_H2V1 = 2,  //yuv 422sp\r
+       IPP_Y_CBCR_H2V2 = 3, //yuv 420sp\r
+       IPP_Y_CBCR_H1V1 =6, //yuv 444sp\r
+       IPP_IMGTYPE_LIMIT\r
+};\r
+\r
+typedef enum\r
+ {\r
+     IPP_ROT_90,\r
+     IPP_ROT_180,\r
+     IPP_ROT_270,\r
+     IPP_ROT_X_FLIP,\r
+     IPP_ROT_Y_FLIP,\r
+     IPP_ROT_0,\r
+     IPP_ROT_LIMIT\r
+ } ROT_DEG;\r
+\r
+ struct ipp_regs {\r
+       uint32_t ipp_config;\r
+       uint32_t ipp_src_img_info;\r
+       uint32_t ipp_dst_img_info;\r
+       uint32_t ipp_img_vir;\r
+       uint32_t ipp_int;\r
+       uint32_t ipp_src0_y_mst;\r
+       uint32_t ipp_src0_Cbr_mst;\r
+       uint32_t ipp_src1_y_mst;\r
+       uint32_t ipp_src1_Cbr_mst;\r
+       uint32_t ipp_dst0_y_mst;\r
+       uint32_t ipp_dst0_Cbr_mst;\r
+       uint32_t ipp_dst1_y_mst;\r
+       uint32_t ipp_dst1_Cbr_mst;\r
+       uint32_t ipp_pre_scl_para;\r
+       uint32_t ipp_post_scl_para;\r
+       uint32_t ipp_swap_ctrl;\r
+       uint32_t ipp_pre_img_info;\r
+       uint32_t ipp_axi_id;\r
+       uint32_t ipp_process_st;\r
+};\r
+\r
+#define IPP_CONFIG                             (0x00)\r
+#define IPP_SRC_IMG_INFO               (0x04)\r
+#define IPP_DST_IMG_INFO               (0x08)\r
+#define IPP_IMG_VIR                            (0x0c)\r
+#define IPP_INT                                        (0x10)\r
+#define IPP_SRC0_Y_MST                 (0x14)\r
+#define IPP_SRC0_CBR_MST               (0x18)\r
+#define IPP_SRC1_Y_MST                 (0x1c)\r
+#define IPP_SRC1_CBR_MST               (0x20)\r
+#define IPP_DST0_Y_MST                 (0x24)\r
+#define IPP_DST0_CBR_MST               (0x28)\r
+#define IPP_DST1_Y_MST                 (0x2c)\r
+#define IPP_DST1_CBR_MST               (0x30)\r
+#define IPP_PRE_SCL_PARA               (0x34)\r
+#define IPP_POST_SCL_PARA              (0x38)\r
+#define IPP_SWAP_CTRL                  (0x3c)\r
+#define IPP_PRE_IMG_INFO               (0x40)\r
+#define IPP_AXI_ID                             (0x44)\r
+#define IPP_SRESET                             (0x48)\r
+#define IPP_PROCESS_ST                 (0x50)\r
+\r
+/*ipp config*/\r
+#define STORE_CLIP_MODE                        (1<<26)\r
+#define DEINTERLACE_ENABLE             (1<<24)\r
+#define ROT_ENABLE                             (1<<8)\r
+#define PRE_SCALE                              (1<<4)\r
+#define POST_SCALE                             (1<<3)\r
+\r
+#define IPP_BLIT_COMPLETE_EVENT BIT(1)\r
+\r
+#define IS_YCRCB(img) ((img == IPP_Y_CBCR_H2V1) | (img == IPP_Y_CBCR_H2V2) | \\r
+                      (img == IPP_Y_CBCR_H1V1) )\r
+#define IS_RGB(img) ((img == IPP_RGB_565) | (img == IPP_ARGB_8888) | \\r
+                    (img == IPP_XRGB_8888) ))\r
+#define HAS_ALPHA(img) (img == IPP_ARGB_8888)\r
+\r
+\r
+int ipp_blit_async(const struct rk29_ipp_req *req);\r
+int ipp_blit_sync(const struct rk29_ipp_req *req);\r
+#endif /*_RK29_IPP_DRIVER_H_*/
\ No newline at end of file