rk30xx: add lpj_gpll init to prevent dma halt and sdio error
authorchenxing <chenxing@rock-chips.com>
Mon, 13 May 2013 02:15:39 +0000 (10:15 +0800)
committerchenxing <chenxing@rock-chips.com>
Mon, 13 May 2013 02:15:39 +0000 (10:15 +0800)
arch/arm/mach-rk30/clock_data-rk3066b.c
arch/arm/mach-rk30/clock_data.c

index abf66390fcdfc02584597bac5c25041e0da7b14a..66a2006b695703cc7bedf091c142bfa5bb89d52e 100644 (file)
@@ -3298,6 +3298,8 @@ static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long
 
        //general
        clk_set_rate_nolock(&general_pll_clk, gpll_rate);
+       lpj_gpll = CLK_LOOPS_RECALC(general_pll_clk.rate);
+
        //code pll
        clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
 
index 0b5a39b529db6370b67b82b0652197699175d616..5643b48e27ab643d3612665c17ee8ccefdb6c9c0 100644 (file)
@@ -3342,6 +3342,8 @@ static void __init rk30_clock_common_init(unsigned long gpll_rate,unsigned long
        clk_set_rate_nolock(&general_pll_clk, 297 * MHZ);
 #endif
        clk_set_rate_nolock(&general_pll_clk, gpll_rate);
+       lpj_gpll = CLK_LOOPS_RECALC(general_pll_clk.rate);
+
        //code pll
        clk_set_rate_nolock(&codec_pll_clk, cpll_rate);