};
};
- vpu: vpu_service@ff650000 {
- compatible = "rockchip,vpu_service";
- rockchip,grf = <&grf>;
- iommus = <&vpu_mmu>;
- iommu_enabled = <1>;
- reg = <0x0 0xff650000 0x0 0x800>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "irq_dec", "irq_enc";
- clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
- reset-names = "video_h", "video_a";
- power-domains = <&power RK3399_PD_VCODEC>;
- name = "vpu_service";
- dev_mode = <0>;
- /* 0 means ion, 1 means drm */
- allocator = <1>;
- status = "disabled";
- };
-
- vpu_mmu: iommu@ff650800 {
- dbgname = "vpu";
- compatible = "rockchip,iommu";
- reg = <0x0 0xff650800 0x0 0x40>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vpu_mmu";
- #iommu-cells = <0>;
- };
-
- rkvdec: rkvdec@ff660000 {
- compatible = "rockchip,rkvdec";
- rockchip,grf = <&grf>;
- iommus = <&vdec_mmu>;
- iommu_enabled = <1>;
- reg = <0x0 0xff660000 0x0 0x400>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "irq_dec";
- clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>;
- clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
- resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
- reset-names = "video_h", "video_a";
- power-domains = <&power RK3399_PD_VDU>;
- dev_mode = <2>;
- name = "rkvdec";
- /* 0 means ion, 1 means drm */
- allocator = <1>;
- status = "disabled";
- };
-
- vdec_mmu: iommu@ff660480 {
- dbgname = "vdec";
- compatible = "rockchip,iommu";
- reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vdec_mmu";
- #iommu-cells = <0>;
- };
-
rga: rga@ff680000 {
compatible = "rockchip,rga2";
dev_mode = <1>;
};
};
- vpu: vpu_service@ff650000 {
- compatible = "rockchip,vpu_service";
- rockchip,grf = <&grf>;
- iommu_enabled = <1>;
- reg = <0x0 0xff650000 0x0 0x800>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "irq_dec", "irq_enc";
- clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
- reset-names = "video_h", "video_a";
- power-domains = <&power RK3399_PD_VCODEC>;
- name = "vpu_service";
- dev_mode = <0>;
- /* 0 means ion, 1 means drm */
- allocator = <0>;
- };
-
- vpu_mmu: vpu_mmu {
- dbgname = "vpu";
- compatible = "rockchip,vpu_mmu";
- reg = <0x0 0xff650800 0x0 0x40>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vpu_mmu";
- };
-
- rkvdec: rkvdec@ff660000 {
- compatible = "rockchip,rkvdec";
- rockchip,grf = <&grf>;
- iommu_enabled = <1>;
- reg = <0x0 0xff660000 0x0 0x400>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "irq_dec";
- clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>;
- clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
- resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
- reset-names = "video_h", "video_a";
- power-domains = <&power RK3399_PD_VDU>;
- dev_mode = <2>;
- name = "rkvdec";
- /* 0 means ion, 1 means drm */
- allocator = <0>;
- };
-
- vdec_mmu: vdec_mmu {
- dbgname = "vdec";
- compatible = "rockchip,vdec_mmu";
- reg = <0x0 0xff660480 0x0 0x40>,
- <0x0 0xff6604c0 0x0 0x40>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vdec_mmu";
- };
-
iep: iep@ff670000 {
compatible = "rockchip,iep";
iommu_enabled = <1>;
};
};
+&vpu {
+ status = "okay";
+ /delete-property/ iommus;
+ /* 0 means ion, 1 means drm */
+ allocator = <0>;
+};
+
+&vpu_mmu {
+ dbgname = "vpu";
+ compatible = "rockchip,vpu_mmu";
+};
+
+&rkvdec {
+ status = "okay";
+ /delete-property/ iommus;
+ /* 0 means ion, 1 means drm */
+ allocator = <0>;
+};
+
+&vdec_mmu {
+ dbgname = "vdec";
+ compatible = "rockchip,vdec_mmu";
+};
+
&pinctrl {
isp {
cif_clkout: cif-clkout {
status = "disabled";
};
+ vpu: vpu_service@ff650000 {
+ compatible = "rockchip,vpu_service";
+ rockchip,grf = <&grf>;
+ iommus = <&vpu_mmu>;
+ iommu_enabled = <1>;
+ reg = <0x0 0xff650000 0x0 0x800>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "irq_dec", "irq_enc";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
+ reset-names = "video_h", "video_a";
+ power-domains = <&power RK3399_PD_VCODEC>;
+ name = "vpu_service";
+ dev_mode = <0>;
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ status = "disabled";
+ };
+
+ vpu_mmu: iommu@ff650800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff650800 0x0 0x40>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vpu_mmu";
+ #iommu-cells = <0>;
+ };
+
+ rkvdec: rkvdec@ff660000 {
+ compatible = "rockchip,rkvdec";
+ rockchip,grf = <&grf>;
+ iommus = <&vdec_mmu>;
+ iommu_enabled = <1>;
+ reg = <0x0 0xff660000 0x0 0x400>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "irq_dec";
+ clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
+ <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
+ clock-names = "aclk_vcodec", "hclk_vcodec",
+ "clk_cabac", "clk_core";
+ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
+ reset-names = "video_h", "video_a";
+ power-domains = <&power RK3399_PD_VDU>;
+ dev_mode = <2>;
+ name = "rkvdec";
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ status = "disabled";
+ };
+
+ vdec_mmu: iommu@ff660480 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vdec_mmu";
+ #iommu-cells = <0>;
+ };
+
rga: rga@ff680000 {
compatible = "rockchip,rk3399-rga";
reg = <0x0 0xff680000 0x0 0x10000>;