arm64: dts: rockchip: add usb3 phy nodes for rk3328

This patch adds USB 3.0 PHY grf node and apb node
for rk3328 USB 3.0 module.

Change-Id: I9d4e6c6d6792ac5fd6c2a4d7cc902f1ff0cf4ef1
Signed-off-by: William Wu <wulf@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index f410ca5a0b4310b7de94479148bbc06c45168025..c854c28a2da3d3e7b12b0e2c082b34f259ecae91 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -506,6 +506,46 @@
                };
        };
 
+       usb3phy_grf: syscon@ff460000 {
+               compatible = "rockchip,usb3phy-grf", "syscon";
+               reg = <0x0 0xff460000 0x0 0x1000>;
+       };
+
+       u3phy: usb3-phy@ff470000 {
+               compatible = "rockchip,rk3328-u3phy";
+               reg = <0x0 0xff470000 0x0 0x0>;
+               rockchip,u3phygrf = <&usb3phy_grf>;
+               interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "linestate";
+               clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
+               clock-names = "u3phy-otg", "u3phy-pipe";
+               resets = <&cru SRST_USB3PHY_U2>,
+                        <&cru SRST_USB3PHY_U3>,
+                        <&cru SRST_USB3PHY_PIPE>,
+                        <&cru SRST_USB3OTG_UTMI>,
+                        <&cru SRST_USB3PHY_OTG_P>,
+                        <&cru SRST_USB3PHY_PIPE_P>;
+               reset-names = "u3phy-u2-por", "u3phy-u3-por",
+                             "u3phy-pipe-mac", "u3phy-utmi-mac",
+                             "u3phy-utmi-apb", "u3phy-pipe-apb";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+               status = "disabled";
+
+               u3phy_utmi: utmi@ff470000 {
+                       reg = <0x0 0xff470000 0x0 0x8000>;
+                       #phy-cells = <0>;
+                       status = "disabled";
+               };
+
+               u3phy_pipe: pipe@ff478000 {
+                       reg = <0x0 0xff478000 0x0 0x8000>;
+                       #phy-cells = <0>;
+                       status = "disabled";
+               };
+       };
+
        sdmmc: rksdmmc@ff500000 {
                compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
                reg = <0x0 0xff500000 0x0 0x4000>;