[InstCombine] Fix SSE2/AVX2 vector logical shift by constant

This patch fixes the sse2/avx2 vector shift by constant instcombine call to correctly deal with the fact that the shift amount is formed from the entire lower 64-bit and not just the lowest element as it currently assumes.

e.g.

%1 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)

In this case, (V)PSRLD doesn't perform a lshr by 15 but in fact attempts to shift by 64424509455 ((15 << 32) | 15) - giving a zero result.

In addition, this review also recognizes shift-by-zero from a ConstantAggregateZero type (PR23821).

Differential Revision: http://reviews.llvm.org/D11760

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244341 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Transforms/InstCombine/InstCombineCalls.cpp b/lib/Transforms/InstCombine/InstCombineCalls.cpp
index 668789b516d0704606936c9a27c7517e6fed7321..de413c423481139f46a785f88df0dea098155327 100644 (file)
--- a/lib/Transforms/InstCombine/InstCombineCalls.cpp
+++ b/lib/Transforms/InstCombine/InstCombineCalls.cpp
@@ -200,33 +200,56 @@ Instruction *InstCombiner::SimplifyMemSet(MemSetInst *MI) {
 static Value *SimplifyX86immshift(const IntrinsicInst &II,
                                   InstCombiner::BuilderTy &Builder,
                                   bool ShiftLeft) {
-  // Simplify if count is constant. To 0 if >= BitWidth,
-  // otherwise to shl/lshr.
-  auto CDV = dyn_cast<ConstantDataVector>(II.getArgOperand(1));
-  auto CInt = dyn_cast<ConstantInt>(II.getArgOperand(1));
-  if (!CDV && !CInt)
+  // Simplify if count is constant.
+  auto Arg1 = II.getArgOperand(1);
+  auto CAZ = dyn_cast<ConstantAggregateZero>(Arg1);
+  auto CDV = dyn_cast<ConstantDataVector>(Arg1);
+  auto CInt = dyn_cast<ConstantInt>(Arg1);
+  if (!CAZ && !CDV && !CInt)
     return nullptr;
-  ConstantInt *Count;
-  if (CDV)
-    Count = cast<ConstantInt>(CDV->getElementAsConstant(0));
-  else
-    Count = CInt;
+
+  APInt Count(64, 0);
+  if (CDV) {
+    // SSE2/AVX2 uses all the first 64-bits of the 128-bit vector
+    // operand to compute the shift amount.
+    auto VT = cast<VectorType>(CDV->getType());
+    unsigned BitWidth = VT->getElementType()->getPrimitiveSizeInBits();
+    assert((64 % BitWidth) == 0 && "Unexpected packed shift size");
+    unsigned NumSubElts = 64 / BitWidth;
+
+    // Concatenate the sub-elements to create the 64-bit value.
+    for (unsigned i = 0; i != NumSubElts; ++i) {
+      unsigned SubEltIdx = (NumSubElts - 1) - i;
+      auto SubElt = cast<ConstantInt>(CDV->getElementAsConstant(SubEltIdx));
+      Count = Count.shl(BitWidth);
+      Count |= SubElt->getValue().zextOrTrunc(64);
+    }
+  }
+  else if (CInt)
+    Count = CInt->getValue();
 
   auto Vec = II.getArgOperand(0);
   auto VT = cast<VectorType>(Vec->getType());
   auto SVT = VT->getElementType();
-  if (Count->getZExtValue() > (SVT->getPrimitiveSizeInBits() - 1))
-    return ConstantAggregateZero::get(VT);
-
   unsigned VWidth = VT->getNumElements();
+  unsigned BitWidth = SVT->getPrimitiveSizeInBits();
+
+  // If shift-by-zero then just return the original value.
+  if (Count == 0)
+    return Vec;
+
+  // Handle cases when Shift >= BitWidth - just return zero.
+  if (Count.uge(BitWidth))
+    return ConstantAggregateZero::get(VT);
 
   // Get a constant vector of the same type as the first operand.
-  auto VTCI = ConstantInt::get(VT->getElementType(), Count->getZExtValue());
+  auto ShiftAmt = ConstantInt::get(SVT, Count.zextOrTrunc(BitWidth));
+  auto ShiftVec = Builder.CreateVectorSplat(VWidth, ShiftAmt);
 
   if (ShiftLeft)
-    return Builder.CreateShl(Vec, Builder.CreateVectorSplat(VWidth, VTCI));
+    return Builder.CreateShl(Vec, ShiftVec);
 
-  return Builder.CreateLShr(Vec, Builder.CreateVectorSplat(VWidth, VTCI));
+  return Builder.CreateLShr(Vec, ShiftVec);
 }
 
 static Value *SimplifyX86extend(const IntrinsicInst &II,

diff --git a/test/Transforms/InstCombine/x86-vector-shifts.ll b/test/Transforms/InstCombine/x86-vector-shifts.ll
index 2bf428ef2ffcb37f40593d4b780cfb7a9ac17aa6..fdfad4900f972fae9a26efcd47afb7593be29762 100644 (file)
--- a/test/Transforms/InstCombine/x86-vector-shifts.ll
+++ b/test/Transforms/InstCombine/x86-vector-shifts.ll
@@ -7,132 +7,132 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 \r
 define <8 x i16> @sse2_psrli_w_0(<8 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psrli_w_0\r
-; CHECK: ret <8 x i16> %v\r
+; CHECK-NEXT: ret <8 x i16> %v\r
   %1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %v, i32 0)\r
   ret <8 x i16> %1\r
 }\r
 \r
 define <8 x i16> @sse2_psrli_w_15(<8 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psrli_w_15\r
-; CHECK: %1 = lshr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
-; CHECK: ret <8 x i16> %1\r
+; CHECK-NEXT: %1 = lshr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
+; CHECK-NEXT: ret <8 x i16> %1\r
   %1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %v, i32 15)\r
   ret <8 x i16> %1\r
 }\r
 \r
 define <8 x i16> @sse2_psrli_w_64(<8 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psrli_w_64\r
-; CHECK: ret <8 x i16> zeroinitializer\r
+; CHECK-NEXT: ret <8 x i16> zeroinitializer\r
   %1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %v, i32 64)\r
   ret <8 x i16> %1\r
 }\r
 \r
 define <4 x i32> @sse2_psrli_d_0(<4 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psrli_d_0\r
-; CHECK: ret <4 x i32> %v\r
+; CHECK-NEXT: ret <4 x i32> %v\r
   %1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %v, i32 0)\r
   ret <4 x i32> %1\r
 }\r
 \r
 define <4 x i32> @sse2_psrli_d_15(<4 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psrli_d_15\r
-; CHECK: %1 = lshr <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>\r
-; CHECK: ret <4 x i32> %1\r
+; CHECK-NEXT: %1 = lshr <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>\r
+; CHECK-NEXT: ret <4 x i32> %1\r
   %1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %v, i32 15)\r
   ret <4 x i32> %1\r
 }\r
 \r
 define <4 x i32> @sse2_psrli_d_64(<4 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psrli_d_64\r
-; CHECK: ret <4 x i32> zeroinitializer\r
+; CHECK-NEXT: ret <4 x i32> zeroinitializer\r
   %1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %v, i32 64)\r
   ret <4 x i32> %1\r
 }\r
 \r
 define <2 x i64> @sse2_psrli_q_0(<2 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psrli_q_0\r
-; CHECK: ret <2 x i64> %v\r
+; CHECK-NEXT: ret <2 x i64> %v\r
   %1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %v, i32 0)\r
   ret <2 x i64> %1\r
 }\r
 \r
 define <2 x i64> @sse2_psrli_q_15(<2 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psrli_q_15\r
-; CHECK: %1 = lshr <2 x i64> %v, <i64 15, i64 15>\r
-; CHECK: ret <2 x i64> %1\r
+; CHECK-NEXT: %1 = lshr <2 x i64> %v, <i64 15, i64 15>\r
+; CHECK-NEXT: ret <2 x i64> %1\r
   %1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %v, i32 15)\r
   ret <2 x i64> %1\r
 }\r
 \r
 define <2 x i64> @sse2_psrli_q_64(<2 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psrli_q_64\r
-; CHECK: ret <2 x i64> zeroinitializer\r
+; CHECK-NEXT: ret <2 x i64> zeroinitializer\r
   %1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %v, i32 64)\r
   ret <2 x i64> %1\r
 }\r
 \r
 define <16 x i16> @avx2_psrli_w_0(<16 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psrli_w_0\r
-; CHECK: ret <16 x i16> %v\r
+; CHECK-NEXT: ret <16 x i16> %v\r
   %1 = tail call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %v, i32 0)\r
   ret <16 x i16> %1\r
 }\r
 \r
 define <16 x i16> @avx2_psrli_w_15(<16 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psrli_w_15\r
-; CHECK: %1 = lshr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
-; CHECK: ret <16 x i16> %1\r
+; CHECK-NEXT: %1 = lshr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
+; CHECK-NEXT: ret <16 x i16> %1\r
   %1 = tail call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %v, i32 15)\r
   ret <16 x i16> %1\r
 }\r
 \r
 define <16 x i16> @avx2_psrli_w_64(<16 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psrli_w_64\r
-; CHECK: ret <16 x i16> zeroinitializer\r
+; CHECK-NEXT: ret <16 x i16> zeroinitializer\r
   %1 = tail call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %v, i32 64)\r
   ret <16 x i16> %1\r
 }\r
 \r
 define <8 x i32> @avx2_psrli_d_0(<8 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psrli_d_0\r
-; CHECK: ret <8 x i32> %v\r
+; CHECK-NEXT: ret <8 x i32> %v\r
   %1 = tail call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %v, i32 0)\r
   ret <8 x i32> %1\r
 }\r
 \r
 define <8 x i32> @avx2_psrli_d_15(<8 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psrli_d_15\r
-; CHECK: %1 = lshr <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>\r
-; CHECK: ret <8 x i32> %1\r
+; CHECK-NEXT: %1 = lshr <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>\r
+; CHECK-NEXT: ret <8 x i32> %1\r
   %1 = tail call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %v, i32 15)\r
   ret <8 x i32> %1\r
 }\r
 \r
 define <8 x i32> @avx2_psrli_d_64(<8 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psrli_d_64\r
-; CHECK: ret <8 x i32> zeroinitializer\r
+; CHECK-NEXT: ret <8 x i32> zeroinitializer\r
   %1 = tail call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %v, i32 64)\r
   ret <8 x i32> %1\r
 }\r
 \r
 define <4 x i64> @avx2_psrli_q_0(<4 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psrli_q_0\r
-; CHECK: ret <4 x i64> %v\r
+; CHECK-NEXT: ret <4 x i64> %v\r
   %1 = tail call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %v, i32 0)\r
   ret <4 x i64> %1\r
 }\r
 \r
 define <4 x i64> @avx2_psrli_q_15(<4 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psrli_q_15\r
-; CHECK: %1 = lshr <4 x i64> %v, <i64 15, i64 15, i64 15, i64 15>\r
-; CHECK: ret <4 x i64> %1\r
+; CHECK-NEXT: %1 = lshr <4 x i64> %v, <i64 15, i64 15, i64 15, i64 15>\r
+; CHECK-NEXT: ret <4 x i64> %1\r
   %1 = tail call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %v, i32 15)\r
   ret <4 x i64> %1\r
 }\r
 \r
 define <4 x i64> @avx2_psrli_q_64(<4 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psrli_q_64\r
-; CHECK: ret <4 x i64> zeroinitializer\r
+; CHECK-NEXT: ret <4 x i64> zeroinitializer\r
   %1 = tail call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %v, i32 64)\r
   ret <4 x i64> %1\r
 }\r
@@ -143,132 +143,132 @@ define <4 x i64> @avx2_psrli_q_64(<4 x i64> %v) nounwind readnone uwtable {
 \r
 define <8 x i16> @sse2_pslli_w_0(<8 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_pslli_w_0\r
-; CHECK: ret <8 x i16> %v\r
+; CHECK-NEXT: ret <8 x i16> %v\r
   %1 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %v, i32 0)\r
   ret <8 x i16> %1\r
 }\r
 \r
 define <8 x i16> @sse2_pslli_w_15(<8 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_pslli_w_15\r
-; CHECK: %1 = shl <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
-; CHECK: ret <8 x i16> %1\r
+; CHECK-NEXT: %1 = shl <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
+; CHECK-NEXT: ret <8 x i16> %1\r
   %1 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %v, i32 15)\r
   ret <8 x i16> %1\r
 }\r
 \r
 define <8 x i16> @sse2_pslli_w_64(<8 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_pslli_w_64\r
-; CHECK: ret <8 x i16> zeroinitializer\r
+; CHECK-NEXT: ret <8 x i16> zeroinitializer\r
   %1 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %v, i32 64)\r
   ret <8 x i16> %1\r
 }\r
 \r
 define <4 x i32> @sse2_pslli_d_0(<4 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_pslli_d_0\r
-; CHECK: ret <4 x i32> %v\r
+; CHECK-NEXT: ret <4 x i32> %v\r
   %1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %v, i32 0)\r
   ret <4 x i32> %1\r
 }\r
 \r
 define <4 x i32> @sse2_pslli_d_15(<4 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_pslli_d_15\r
-; CHECK: %1 = shl <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>\r
-; CHECK: ret <4 x i32> %1\r
+; CHECK-NEXT: %1 = shl <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>\r
+; CHECK-NEXT: ret <4 x i32> %1\r
   %1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %v, i32 15)\r
   ret <4 x i32> %1\r
 }\r
 \r
 define <4 x i32> @sse2_pslli_d_64(<4 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_pslli_d_64\r
-; CHECK: ret <4 x i32> zeroinitializer\r
+; CHECK-NEXT: ret <4 x i32> zeroinitializer\r
   %1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %v, i32 64)\r
   ret <4 x i32> %1\r
 }\r
 \r
 define <2 x i64> @sse2_pslli_q_0(<2 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_pslli_q_0\r
-; CHECK: ret <2 x i64> %v\r
+; CHECK-NEXT: ret <2 x i64> %v\r
   %1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %v, i32 0)\r
   ret <2 x i64> %1\r
 }\r
 \r
 define <2 x i64> @sse2_pslli_q_15(<2 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_pslli_q_15\r
-; CHECK: %1 = shl <2 x i64> %v, <i64 15, i64 15>\r
-; CHECK: ret <2 x i64> %1\r
+; CHECK-NEXT: %1 = shl <2 x i64> %v, <i64 15, i64 15>\r
+; CHECK-NEXT: ret <2 x i64> %1\r
   %1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %v, i32 15)\r
   ret <2 x i64> %1\r
 }\r
 \r
 define <2 x i64> @sse2_pslli_q_64(<2 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_pslli_q_64\r
-; CHECK: ret <2 x i64> zeroinitializer\r
+; CHECK-NEXT: ret <2 x i64> zeroinitializer\r
   %1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %v, i32 64)\r
   ret <2 x i64> %1\r
 }\r
 \r
 define <16 x i16> @avx2_pslli_w_0(<16 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_pslli_w_0\r
-; CHECK: ret <16 x i16> %v\r
+; CHECK-NEXT: ret <16 x i16> %v\r
   %1 = tail call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %v, i32 0)\r
   ret <16 x i16> %1\r
 }\r
 \r
 define <16 x i16> @avx2_pslli_w_15(<16 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_pslli_w_15\r
-; CHECK: %1 = shl <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
-; CHECK: ret <16 x i16> %1\r
+; CHECK-NEXT: %1 = shl <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
+; CHECK-NEXT: ret <16 x i16> %1\r
   %1 = tail call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %v, i32 15)\r
   ret <16 x i16> %1\r
 }\r
 \r
 define <16 x i16> @avx2_pslli_w_64(<16 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_pslli_w_64\r
-; CHECK: ret <16 x i16> zeroinitializer\r
+; CHECK-NEXT: ret <16 x i16> zeroinitializer\r
   %1 = tail call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %v, i32 64)\r
   ret <16 x i16> %1\r
 }\r
 \r
 define <8 x i32> @avx2_pslli_d_0(<8 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_pslli_d_0\r
-; CHECK: ret <8 x i32> %v\r
+; CHECK-NEXT: ret <8 x i32> %v\r
   %1 = tail call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %v, i32 0)\r
   ret <8 x i32> %1\r
 }\r
 \r
 define <8 x i32> @avx2_pslli_d_15(<8 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_pslli_d_15\r
-; CHECK: %1 = shl <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>\r
-; CHECK: ret <8 x i32> %1\r
+; CHECK-NEXT: %1 = shl <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>\r
+; CHECK-NEXT: ret <8 x i32> %1\r
   %1 = tail call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %v, i32 15)\r
   ret <8 x i32> %1\r
 }\r
 \r
 define <8 x i32> @avx2_pslli_d_64(<8 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_pslli_d_64\r
-; CHECK: ret <8 x i32> zeroinitializer\r
+; CHECK-NEXT: ret <8 x i32> zeroinitializer\r
   %1 = tail call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %v, i32 64)\r
   ret <8 x i32> %1\r
 }\r
 \r
 define <4 x i64> @avx2_pslli_q_0(<4 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_pslli_q_0\r
-; CHECK: ret <4 x i64> %v\r
+; CHECK-NEXT: ret <4 x i64> %v\r
   %1 = tail call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %v, i32 0)\r
   ret <4 x i64> %1\r
 }\r
 \r
 define <4 x i64> @avx2_pslli_q_15(<4 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_pslli_q_15\r
-; CHECK: %1 = shl <4 x i64> %v, <i64 15, i64 15, i64 15, i64 15>\r
-; CHECK: ret <4 x i64> %1\r
+; CHECK-NEXT: %1 = shl <4 x i64> %v, <i64 15, i64 15, i64 15, i64 15>\r
+; CHECK-NEXT: ret <4 x i64> %1\r
   %1 = tail call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %v, i32 15)\r
   ret <4 x i64> %1\r
 }\r
 \r
 define <4 x i64> @avx2_pslli_q_64(<4 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_pslli_q_64\r
-; CHECK: ret <4 x i64> zeroinitializer\r
+; CHECK-NEXT: ret <4 x i64> zeroinitializer\r
   %1 = tail call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %v, i32 64)\r
   ret <4 x i64> %1\r
 }\r
@@ -277,92 +277,162 @@ define <4 x i64> @avx2_pslli_q_64(<4 x i64> %v) nounwind readnone uwtable {
 ; LSHR - Constant Vector\r
 ;\r
 \r
+define <8 x i16> @sse2_psrl_w_0(<8 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psrl_w_0\r
+; CHECK-NEXT: ret <8 x i16> %v\r
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %v, <8 x i16> zeroinitializer)\r
+  ret <8 x i16> %1\r
+}\r
+\r
 define <8 x i16> @sse2_psrl_w_15(<8 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psrl_w_15\r
-; CHECK: %1 = lshr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
-; CHECK: ret <8 x i16> %1\r
+; CHECK-NEXT: %1 = lshr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
+; CHECK-NEXT: ret <8 x i16> %1\r
   %1 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %v, <8 x i16> <i16 15, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)\r
   ret <8 x i16> %1\r
 }\r
 \r
+define <8 x i16> @sse2_psrl_w_15_splat(<8 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psrl_w_15_splat\r
+; CHECK-NEXT: ret <8 x i16> zeroinitializer\r
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %v, <8 x i16> <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>)\r
+  ret <8 x i16> %1\r
+}\r
+\r
 define <8 x i16> @sse2_psrl_w_64(<8 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psrl_w_64\r
-; CHECK: ret <8 x i16> zeroinitializer\r
+; CHECK-NEXT: ret <8 x i16> zeroinitializer\r
   %1 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %v, <8 x i16> <i16 64, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)\r
   ret <8 x i16> %1\r
 }\r
 \r
+define <4 x i32> @sse2_psrl_d_0(<4 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psrl_d_0\r
+; CHECK-NEXT: ret <4 x i32> %v\r
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> zeroinitializer)\r
+  ret <4 x i32> %1\r
+}\r
+\r
 define <4 x i32> @sse2_psrl_d_15(<4 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psrl_d_15\r
-; CHECK: %1 = lshr <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>\r
-; CHECK: ret <4 x i32> %1\r
+; CHECK-NEXT: %1 = lshr <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>\r
+; CHECK-NEXT: ret <4 x i32> %1\r
   %1 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> <i32 15, i32 0, i32 9999, i32 9999>)\r
   ret <4 x i32> %1\r
 }\r
 \r
+define <4 x i32> @sse2_psrl_d_15_splat(<4 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psrl_d_15_splat\r
+; CHECK-NEXT: ret <4 x i32> zeroinitializer\r
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)\r
+  ret <4 x i32> %1\r
+}\r
+\r
 define <4 x i32> @sse2_psrl_d_64(<4 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psrl_d_64\r
-; CHECK: ret <4 x i32> zeroinitializer\r
+; CHECK-NEXT: ret <4 x i32> zeroinitializer\r
   %1 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> <i32 64, i32 0, i32 9999, i32 9999>)\r
   ret <4 x i32> %1\r
 }\r
 \r
+define <2 x i64> @sse2_psrl_q_0(<2 x i64> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psrl_q_0\r
+; CHECK-NEXT: ret <2 x i64> %v\r
+  %1 = tail call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %v, <2 x i64> zeroinitializer)\r
+  ret <2 x i64> %1\r
+}\r
+\r
 define <2 x i64> @sse2_psrl_q_15(<2 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psrl_q_15\r
-; CHECK: %1 = lshr <2 x i64> %v, <i64 15, i64 15>\r
-; CHECK: ret <2 x i64> %1\r
+; CHECK-NEXT: %1 = lshr <2 x i64> %v, <i64 15, i64 15>\r
+; CHECK-NEXT: ret <2 x i64> %1\r
   %1 = tail call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %v, <2 x i64> <i64 15, i64 9999>)\r
   ret <2 x i64> %1\r
 }\r
 \r
 define <2 x i64> @sse2_psrl_q_64(<2 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psrl_q_64\r
-; CHECK: ret <2 x i64> zeroinitializer\r
+; CHECK-NEXT: ret <2 x i64> zeroinitializer\r
   %1 = tail call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %v, <2 x i64> <i64 64, i64 9999>)\r
   ret <2 x i64> %1\r
 }\r
 \r
+define <16 x i16> @avx2_psrl_w_0(<16 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psrl_w_0\r
+; CHECK-NEXT: ret <16 x i16> %v\r
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %v, <8 x i16> zeroinitializer)\r
+  ret <16 x i16> %1\r
+}\r
+\r
 define <16 x i16> @avx2_psrl_w_15(<16 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psrl_w_15\r
-; CHECK: %1 = lshr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
-; CHECK: ret <16 x i16> %1\r
+; CHECK-NEXT: %1 = lshr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
+; CHECK-NEXT: ret <16 x i16> %1\r
   %1 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %v, <8 x i16> <i16 15, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)\r
   ret <16 x i16> %1\r
 }\r
 \r
+define <16 x i16> @avx2_psrl_w_15_splat(<16 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psrl_w_15_splat\r
+; CHECK-NEXT: ret <16 x i16> zeroinitializer\r
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %v, <8 x i16> <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>)\r
+  ret <16 x i16> %1\r
+}\r
+\r
 define <16 x i16> @avx2_psrl_w_64(<16 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psrl_w_64\r
-; CHECK: ret <16 x i16> zeroinitializer\r
+; CHECK-NEXT: ret <16 x i16> zeroinitializer\r
   %1 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %v, <8 x i16> <i16 64, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)\r
   ret <16 x i16> %1\r
 }\r
 \r
+define <8 x i32> @avx2_psrl_d_0(<8 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psrl_d_0\r
+; CHECK-NEXT: ret <8 x i32> %v\r
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %v, <4 x i32> zeroinitializer)\r
+  ret <8 x i32> %1\r
+}\r
+\r
 define <8 x i32> @avx2_psrl_d_15(<8 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psrl_d_15\r
-; CHECK: %1 = lshr <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>\r
-; CHECK: ret <8 x i32> %1\r
+; CHECK-NEXT: %1 = lshr <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>\r
+; CHECK-NEXT: ret <8 x i32> %1\r
   %1 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %v, <4 x i32> <i32 15, i32 0, i32 9999, i32 9999>)\r
   ret <8 x i32> %1\r
 }\r
 \r
+define <8 x i32> @avx2_psrl_d_15_splat(<8 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psrl_d_15_splat\r
+; CHECK-NEXT: ret <8 x i32> zeroinitializer\r
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)\r
+  ret <8 x i32> %1\r
+}\r
+\r
 define <8 x i32> @avx2_psrl_d_64(<8 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psrl_d_64\r
-; CHECK: ret <8 x i32> zeroinitializer\r
+; CHECK-NEXT: ret <8 x i32> zeroinitializer\r
   %1 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %v, <4 x i32> <i32 64, i32 0, i32 9999, i32 9999>)\r
   ret <8 x i32> %1\r
 }\r
 \r
+define <4 x i64> @avx2_psrl_q_0(<4 x i64> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psrl_q_0\r
+; CHECK-NEXT: ret <4 x i64> %v\r
+  %1 = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %v, <2 x i64> zeroinitializer)\r
+  ret <4 x i64> %1\r
+}\r
+\r
 define <4 x i64> @avx2_psrl_q_15(<4 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psrl_q_15\r
-; CHECK: %1 = lshr <4 x i64> %v, <i64 15, i64 15, i64 15, i64 15>\r
-; CHECK: ret <4 x i64> %1\r
+; CHECK-NEXT: %1 = lshr <4 x i64> %v, <i64 15, i64 15, i64 15, i64 15>\r
+; CHECK-NEXT: ret <4 x i64> %1\r
   %1 = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %v, <2 x i64> <i64 15, i64 9999>)\r
   ret <4 x i64> %1\r
 }\r
 \r
 define <4 x i64> @avx2_psrl_q_64(<4 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psrl_q_64\r
-; CHECK: ret <4 x i64> zeroinitializer\r
+; CHECK-NEXT: ret <4 x i64> zeroinitializer\r
   %1 = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %v, <2 x i64> <i64 64, i64 9999>)\r
   ret <4 x i64> %1\r
 }\r
@@ -371,92 +441,162 @@ define <4 x i64> @avx2_psrl_q_64(<4 x i64> %v) nounwind readnone uwtable {
 ; SHL - Constant Vector\r
 ;\r
 \r
+define <8 x i16> @sse2_psll_w_0(<8 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psll_w_0\r
+; CHECK-NEXT: ret <8 x i16> %v\r
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %v, <8 x i16> zeroinitializer)\r
+  ret <8 x i16> %1\r
+}\r
+\r
 define <8 x i16> @sse2_psll_w_15(<8 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psll_w_15\r
-; CHECK: %1 = shl <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
-; CHECK: ret <8 x i16> %1\r
+; CHECK-NEXT: %1 = shl <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
+; CHECK-NEXT: ret <8 x i16> %1\r
   %1 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %v, <8 x i16> <i16 15, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)\r
   ret <8 x i16> %1\r
 }\r
 \r
+define <8 x i16> @sse2_psll_w_15_splat(<8 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psll_w_15_splat\r
+; CHECK-NEXT: ret <8 x i16> zeroinitializer\r
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %v, <8 x i16> <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>)\r
+  ret <8 x i16> %1\r
+}\r
+\r
 define <8 x i16> @sse2_psll_w_64(<8 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psll_w_64\r
-; CHECK: ret <8 x i16> zeroinitializer\r
+; CHECK-NEXT: ret <8 x i16> zeroinitializer\r
   %1 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %v, <8 x i16> <i16 64, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)\r
   ret <8 x i16> %1\r
 }\r
 \r
+define <4 x i32> @sse2_psll_d_0(<4 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psll_d_0\r
+; CHECK-NEXT: ret <4 x i32> %v\r
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %v, <4 x i32> zeroinitializer)\r
+  ret <4 x i32> %1\r
+}\r
+\r
 define <4 x i32> @sse2_psll_d_15(<4 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psll_d_15\r
-; CHECK: %1 = shl <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>\r
-; CHECK: ret <4 x i32> %1\r
+; CHECK-NEXT: %1 = shl <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>\r
+; CHECK-NEXT: ret <4 x i32> %1\r
   %1 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %v, <4 x i32> <i32 15, i32 0, i32 9999, i32 9999>)\r
   ret <4 x i32> %1\r
 }\r
 \r
+define <4 x i32> @sse2_psll_d_15_splat(<4 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psll_d_15_splat\r
+; CHECK-NEXT: ret <4 x i32> zeroinitializer\r
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)\r
+  ret <4 x i32> %1\r
+}\r
+\r
 define <4 x i32> @sse2_psll_d_64(<4 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psll_d_64\r
-; CHECK: ret <4 x i32> zeroinitializer\r
+; CHECK-NEXT: ret <4 x i32> zeroinitializer\r
   %1 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %v, <4 x i32> <i32 64, i32 0, i32 9999, i32 9999>)\r
   ret <4 x i32> %1\r
 }\r
 \r
+define <2 x i64> @sse2_psll_q_0(<2 x i64> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psll_q_0\r
+; CHECK-NEXT: ret <2 x i64> %v\r
+  %1 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %v, <2 x i64> zeroinitializer)\r
+  ret <2 x i64> %1\r
+}\r
+\r
 define <2 x i64> @sse2_psll_q_15(<2 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psll_q_15\r
-; CHECK: %1 = shl <2 x i64> %v, <i64 15, i64 15>\r
-; CHECK: ret <2 x i64> %1\r
+; CHECK-NEXT: %1 = shl <2 x i64> %v, <i64 15, i64 15>\r
+; CHECK-NEXT: ret <2 x i64> %1\r
   %1 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %v, <2 x i64> <i64 15, i64 9999>)\r
   ret <2 x i64> %1\r
 }\r
 \r
 define <2 x i64> @sse2_psll_q_64(<2 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @sse2_psll_q_64\r
-; CHECK: ret <2 x i64> zeroinitializer\r
+; CHECK-NEXT: ret <2 x i64> zeroinitializer\r
   %1 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %v, <2 x i64> <i64 64, i64 9999>)\r
   ret <2 x i64> %1\r
 }\r
 \r
+define <16 x i16> @avx2_psll_w_0(<16 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psll_w_0\r
+; CHECK-NEXT: ret <16 x i16> %v\r
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %v, <8 x i16> zeroinitializer)\r
+  ret <16 x i16> %1\r
+}\r
+\r
 define <16 x i16> @avx2_psll_w_15(<16 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psll_w_15\r
-; CHECK: %1 = shl <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
-; CHECK: ret <16 x i16> %1\r
+; CHECK-NEXT: %1 = shl <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
+; CHECK-NEXT: ret <16 x i16> %1\r
   %1 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %v, <8 x i16> <i16 15, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)\r
   ret <16 x i16> %1\r
 }\r
 \r
+define <16 x i16> @avx2_psll_w_15_splat(<16 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psll_w_15_splat\r
+; CHECK-NEXT: ret <16 x i16> zeroinitializer\r
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %v, <8 x i16> <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>)\r
+  ret <16 x i16> %1\r
+}\r
+\r
 define <16 x i16> @avx2_psll_w_64(<16 x i16> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psll_w_64\r
-; CHECK: ret <16 x i16> zeroinitializer\r
+; CHECK-NEXT: ret <16 x i16> zeroinitializer\r
   %1 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %v, <8 x i16> <i16 64, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)\r
   ret <16 x i16> %1\r
 }\r
 \r
+define <8 x i32> @avx2_psll_d_0(<8 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psll_d_0\r
+; CHECK-NEXT: ret <8 x i32> %v\r
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %v, <4 x i32> zeroinitializer)\r
+  ret <8 x i32> %1\r
+}\r
+\r
 define <8 x i32> @avx2_psll_d_15(<8 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psll_d_15\r
-; CHECK: %1 = shl <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>\r
-; CHECK: ret <8 x i32> %1\r
+; CHECK-NEXT: %1 = shl <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>\r
+; CHECK-NEXT: ret <8 x i32> %1\r
   %1 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %v, <4 x i32> <i32 15, i32 0, i32 9999, i32 9999>)\r
   ret <8 x i32> %1\r
 }\r
 \r
+define <8 x i32> @avx2_psll_d_15_splat(<8 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psll_d_15_splat\r
+; CHECK-NEXT: ret <8 x i32> zeroinitializer\r
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)\r
+  ret <8 x i32> %1\r
+}\r
+\r
 define <8 x i32> @avx2_psll_d_64(<8 x i32> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psll_d_64\r
-; CHECK: ret <8 x i32> zeroinitializer\r
+; CHECK-NEXT: ret <8 x i32> zeroinitializer\r
   %1 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %v, <4 x i32> <i32 64, i32 0, i32 9999, i32 9999>)\r
   ret <8 x i32> %1\r
 }\r
 \r
+define <4 x i64> @avx2_psll_q_0(<4 x i64> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psll_q_0\r
+; CHECK-NEXT: ret <4 x i64> %v\r
+  %1 = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %v, <2 x i64> zeroinitializer)\r
+  ret <4 x i64> %1\r
+}\r
+\r
 define <4 x i64> @avx2_psll_q_15(<4 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psll_q_15\r
-; CHECK: %1 = shl <4 x i64> %v, <i64 15, i64 15, i64 15, i64 15>\r
-; CHECK: ret <4 x i64> %1\r
+; CHECK-NEXT: %1 = shl <4 x i64> %v, <i64 15, i64 15, i64 15, i64 15>\r
+; CHECK-NEXT: ret <4 x i64> %1\r
   %1 = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %v, <2 x i64> <i64 15, i64 9999>)\r
   ret <4 x i64> %1\r
 }\r
 \r
 define <4 x i64> @avx2_psll_q_64(<4 x i64> %v) nounwind readnone uwtable {\r
 ; CHECK-LABEL: @avx2_psll_q_64\r
-; CHECK: ret <4 x i64> zeroinitializer\r
+; CHECK-NEXT: ret <4 x i64> zeroinitializer\r
   %1 = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %v, <2 x i64> <i64 64, i64 9999>)\r
   ret <4 x i64> %1\r
 }\r
@@ -660,6 +800,7 @@ declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32) #1
 declare <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64>, <2 x i64>) #1\r
 declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) #1\r
 declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) #1\r
+\r
 declare <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64>, i32) #1\r
 declare <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32>, i32) #1\r
 declare <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16>, i32) #1\r