ARM STR(immediate) assembly parsing and encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137331 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 8c425545567352d23c59808c057279d19f8513b9..9866a2655825a6a5088cce5df39ad2f102972af1 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -2191,11 +2191,12 @@ multiclass AI2_stridx<bit isByte, string opc, InstrItinClass itin> {
     let Inst{23}    = addr{12};     // U (add = ('U' == 1))
     let Inst{19-16} = addr{16-13};  // Rn
     let Inst{11-0}  = addr{11-0};   // imm12
-    let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
+    let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
   }
 
   def _PRE_REG  : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
-                      (ins GPR:$Rt, addrmode2:$addr), IndexModePre, StFrm, itin,
+                      (ins GPR:$Rt, ldst_so_reg:$addr),
+                      IndexModePre, StFrm, itin,
                       opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
     bits<17> addr;
     let Inst{25} = 1;

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 806c384bea96b00cdd538f3b1560eb0c180253cb..31d2b807edf7da112b54964b6198b0f70fb751ae 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -119,6 +119,8 @@ class ARMAsmParser : public MCTargetAsmParser {
   // Asm Match Converter Methods
   bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
                                   const SmallVectorImpl<MCParsedAsmOperand*> &);
+  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
+                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
   bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
                                   const SmallVectorImpl<MCParsedAsmOperand*> &);
   bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
@@ -2100,6 +2102,20 @@ cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
   return true;
 }
 
+/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
+/// Needed here because the Asm Gen Matcher can't handle properly tied operands
+/// when they refer multiple MIOperands inside a single one.
+bool ARMAsmParser::
+cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
+                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+  // Create a writeback register dummy placeholder.
+  Inst.addOperand(MCOperand::CreateImm(0));
+  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
+  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
+  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
+  return true;
+}
+
 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
 /// when they refer multiple MIOperands inside a single one.
@@ -2108,7 +2124,9 @@ cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
                          const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
   // Create a writeback register dummy placeholder.
   Inst.addOperand(MCOperand::CreateImm(0));
-  assert(0 && "cvtStWriteBackRegAddrMode2 not implemented yet!");
+  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
+  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
+  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
   return true;
 }
 

diff --git a/test/MC/ARM/arm-memory-instructions.s b/test/MC/ARM/arm-memory-instructions.s
index e011718b5a4f8b272281bb073976834dddc6015f..92180a0e54c5f5a0e27c7ded341211832de6d482 100644 (file)
--- a/test/MC/ARM/arm-memory-instructions.s
+++ b/test/MC/ARM/arm-memory-instructions.s
@@ -293,3 +293,17 @@ _func:
 @ CHECK: ldrsht        r2, [r1], -r4           @ encoding: [0xf4,0x20,0x31,0xe0]
 
 
+@------------------------------------------------------------------------------
+@ STR (immediate)
+@------------------------------------------------------------------------------
+        str r8, [r12]
+        str r7, [r1, #12]
+        str r3, [r5, #40]!
+        str r9, [sp], #4095
+        str r1, [r7], #-128
+
+@ CHECK: str   r8, [r12]               @ encoding: [0x00,0x80,0x8c,0xe5]
+@ CHECK: str   r7, [r1, #12]           @ encoding: [0x0c,0x70,0x81,0xe5]
+@ CHECK: str   r3, [r5, #40]!          @ encoding: [0x28,0x30,0xa5,0xe5]
+@ CHECK: str   r9, [sp], #4095         @ encoding: [0xff,0x9f,0x8d,0xe4]
+@ CHECK: str   r1, [r7], #-128         @ encoding: [0x80,0x10,0x07,0xe4]

diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s
index 2cec28494548af6a2fcd1bae5cfb876f646bb35b..1ab1931acc5098a39304863a926fdc02a40e5e2f 100644 (file)
--- a/test/MC/ARM/basic-arm-instructions.s
+++ b/test/MC/ARM/basic-arm-instructions.s
@@ -1854,9 +1854,6 @@ Lforward:
 @ CHECK: stmdb r0!, {r1, r5, r7, sp}   @ encoding: [0xa2,0x20,0x20,0xe9]
 
 
-@------------------------------------------------------------------------------
-@ FIXME:STR*
-@------------------------------------------------------------------------------
 @------------------------------------------------------------------------------
 @ STREX/STREXB/STREXH/STREXD
 @------------------------------------------------------------------------------