Like the comment says, prefer to use the implicit add done by [r+r] addressing

modes than emitting an explicit add and using a base of r0.  This implements
Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27068 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 459ddfaeb8e02d3410a40e52cf48adbb62442651..2941b3426606c0abd301ac77fed76d9b94cf8f52 100644 (file)
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -616,11 +616,21 @@ bool PPCDAGToDAGISel::SelectAddrIdxOnly(SDOperand N, SDOperand &Base,
   // Check to see if we can easily represent this as an [r+r] address.  This
   // will fail if it thinks that the address is more profitably represented as
   // reg+imm, e.g. where imm = 0.
-  if (!SelectAddrIdx(N, Base, Index)) {
-    // Nope, do it the hard way.
-    Base = CurDAG->getRegister(PPC::R0, MVT::i32);
-    Index = N;
+  if (SelectAddrIdx(N, Base, Index))
+    return true;
+  
+  // If the operand is an addition, always emit this as [r+r], since this is
+  // better (for code size, and execution, as the memop does the add for free)
+  // than emitting an explicit add.
+  if (N.getOpcode() == ISD::ADD) {
+    Base = N.getOperand(0);
+    Index = N.getOperand(1);
+    return true;
   }
+  
+  // Otherwise, do it the hard way, using R0 as the base register.
+  Base = CurDAG->getRegister(PPC::R0, MVT::i32);
+  Index = N;
   return true;
 }