Cortex-R4F TRM states that fpu supports both single and double precision.
This patch corrects the information in ARM.td file and corresponding test.
Reviewers: rengolin
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10763
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240776
91177308-0d34-0410-b5e6-
96231b3b80d8
def : ProcessorModel<"cortex-r4f", CortexA8Model,
[ProcR4,
FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
- FeatureVFP3, FeatureVFPOnlySP, FeatureD16]>;
+ FeatureVFP3, FeatureD16]>;
// FIXME: R5 has currently the same ProcessorModel as A8.
def : ProcessorModel<"cortex-r5", CortexA8Model,
; CORTEX-R4F: .eabi_attribute 23, 3
; CORTEX-R4F: .eabi_attribute 24, 1
; CORTEX-R4F: .eabi_attribute 25, 1
-; CORTEX-R4F: .eabi_attribute 27, 1
+; CORTEX-R4F-NOT: .eabi_attribute 27, 1
; CORTEX-R4F-NOT: .eabi_attribute 28
; CORTEX-R4F-NOT: .eabi_attribute 36
; CORTEX-R4F: .eabi_attribute 38, 1