gpio0: gpio0@ff750000 {
compatible = "rockchip,rk3288-gpio-bank0";
reg = <0xff750000 0x100>,
- <0xff730084 0x10>,
+ <0xff730084 0x0c>,
<0xff730064 0x0c>,
<0xff730070 0x0c>;
reg-names = "base", "mux_bank0", "pull_bank0", "drv_bank0";
len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len,
"=================================\n");
- for(i=0; i<0x10; i=i+4)
+ for(i=0; i<0x0c; i=i+4)
{
value = readl_relaxed(bank0->reg_mux_bank0 + i);
len += snprintf(buf + len, PINCTRL_REGS_BUFSIZE - len, "MUX_BANK0[0x%p+0x%x]=0x%08x\n",(int *)bank0->reg_mux_bank0, i, value);
case 0:
//pmu
reg = bank->reg_mux_bank0;
- bits = 2;
+ if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b) || (m.mux.goff == 0x0c))
+ {
+ bits = 2;
+ }
rk32_iomux_bit_op(bank, pin, mux, reg, bits);
break;
#define GPIO0_C2 0x0c20
-
-/* GPIO0_D */
-#define GPIO0_D0 0x0d00
-#define LCDC0_HSYNC_GPIO0D 0x0d01
-
-#define GPIO0_D1 0x0d10
-#define LCDC0_VSYNC_GPIO0D 0x0d11
-
-#define GPIO0_D2 0x0d20
-#define LCDC0_DEN_GPIO0D 0x0d21
-
-#define GPIO0_D3 0x0d30
-#define LCDC0_DCLK_GPIO0D 0x0d31
-
-
/* GPIO1_A */
/* GPIO1_B */
/* GPIO1_C */
#define RK3288_GRF_GPIO0_A_IOMUX 0x0084
#define RK3288_GRF_GPIO0_B_IOMUX 0x0088
#define RK3288_GRF_GPIO0_C_IOMUX 0x008c
-#define RK3288_GRF_GPIO0_D_IOMUX 0x0090
#define RK3288_GRF_GPIO1D_IOMUX 0x000c
#define RK3288_GRF_GPIO2A_IOMUX 0x0010