rk3066b: fix pll wait lock shift error

diff --git a/arch/arm/mach-rk30/clock_data-rk3066b.c b/arch/arm/mach-rk30/clock_data-rk3066b.c
index 819d3731b6d99d46a1aaf1b2a2093a4bdef695ec..a88ce29d7ec0a4774dbf648415707b3c4d0a0f36 100644 (file)
--- a/arch/arm/mach-rk30/clock_data-rk3066b.c
+++ b/arch/arm/mach-rk30/clock_data-rk3066b.c
@@ -524,7 +524,7 @@ static int frac_div_get_seting(unsigned long rate_out, unsigned long rate,
 static void pll_wait_lock(int pll_idx)
 {
        u32 pll_state[4] = {1, 0, 2, 3};
-       u32 bit = 0x10u << pll_state[pll_idx];
+       u32 bit = 0x20u << pll_state[pll_idx];
        int delay = 24000000;
        while (delay > 0) {
                if (regfile_readl(GRF_SOC_STATUS0) & bit)