Rename the IMULri* instructions to IMULrri, as they are actually three address

instructions.  Add forms of these instructions that read from memory

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11518 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp
index ed61165b7e5f97f2036024a333d96aae0d161504..14089b9abb6f78989c57c5636fc606e765aa97f5 100644 (file)
--- a/lib/Target/X86/InstSelectSimple.cpp
+++ b/lib/Target/X86/InstSelectSimple.cpp
@@ -1524,10 +1524,10 @@ void ISel::doMultiplyConst(MachineBasicBlock *MBB,
   }
   
   if (Class == cShort) {
-    BMI(MBB, IP, X86::IMULri16, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
+    BMI(MBB, IP, X86::IMULrri16, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
     return;
   } else if (Class == cInt) {
-    BMI(MBB, IP, X86::IMULri32, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
+    BMI(MBB, IP, X86::IMULrri32, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
     return;
   }
 

diff --git a/lib/Target/X86/PeepholeOptimizer.cpp b/lib/Target/X86/PeepholeOptimizer.cpp
index accbdd6dccb0e5d1cb9395be5609817f5d004506..512a72136693ca24ee1d59f6192fc3b5a845eccc 100644 (file)
--- a/lib/Target/X86/PeepholeOptimizer.cpp
+++ b/lib/Target/X86/PeepholeOptimizer.cpp
@@ -72,7 +72,7 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
     // immediate despite the fact that the operands are 16 or 32 bits.  Because
     // this can save three bytes of code size (and icache space), we want to
     // shrink them if possible.
-  case X86::IMULri16: case X86::IMULri32:
+  case X86::IMULrri16: case X86::IMULrri32:
     assert(MI->getNumOperands() == 3 && "These should all have 3 operands!");
     if (MI->getOperand(2).isImmediate()) {
       int Val = MI->getOperand(2).getImmedValue();
@@ -81,8 +81,8 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
         unsigned Opcode;
         switch (MI->getOpcode()) {
         default: assert(0 && "Unknown opcode value!");
-        case X86::IMULri16: Opcode = X86::IMULri16b; break;
-        case X86::IMULri32: Opcode = X86::IMULri32b; break;
+        case X86::IMULrri16: Opcode = X86::IMULrri16b; break;
+        case X86::IMULrri32: Opcode = X86::IMULrri32b; break;
         }
         unsigned R0 = MI->getOperand(0).getReg();
         unsigned R1 = MI->getOperand(1).getReg();
@@ -93,6 +93,31 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
     }
     return false;
 
+  case X86::IMULrmi16: case X86::IMULrmi32:
+    assert(MI->getNumOperands() == 6 && "These should all have 6 operands!");
+    if (MI->getOperand(5).isImmediate()) {
+      int Val = MI->getOperand(5).getImmedValue();
+      // If the value is the same when signed extended from 8 bits...
+      if (Val == (signed int)(signed char)Val) {
+        unsigned Opcode;
+        switch (MI->getOpcode()) {
+        default: assert(0 && "Unknown opcode value!");
+        case X86::IMULrmi16: Opcode = X86::IMULrmi16b; break;
+        case X86::IMULrmi32: Opcode = X86::IMULrmi32b; break;
+        }
+        unsigned R0 = MI->getOperand(0).getReg();
+        unsigned R1 = MI->getOperand(1).getReg();
+        unsigned Scale = MI->getOperand(2).getImmedValue();
+        unsigned R2 = MI->getOperand(3).getReg();
+        unsigned Offset = MI->getOperand(3).getImmedValue();
+        I = MBB.insert(MBB.erase(I),
+                       BuildMI(Opcode, 2, R0).addReg(R1).addZImm(Scale).
+                             addReg(R2).addSImm(Offset).addZImm((char)Val));
+        return true;
+      }
+    }
+    return false;
+
   case X86::ADDri16:  case X86::ADDri32:
   case X86::ADDmi16:  case X86::ADDmi32:
   case X86::SUBri16:  case X86::SUBri32:

diff --git a/lib/Target/X86/Printer.cpp b/lib/Target/X86/Printer.cpp
index 31ac00f7293740a72d98dbca29b7a651cf42c50e..f19b3422ae20d8d6e1e858a200bce6ba9822997e 100644 (file)
--- a/lib/Target/X86/Printer.cpp
+++ b/lib/Target/X86/Printer.cpp
@@ -665,7 +665,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
     // like: add r32, r/m32
     //
     // 3 Operands: in this form, we can have 'INST R1, R2, imm', which is used
-    // for instructions like the IMULri instructions.
+    // for instructions like the IMULrri instructions.
     //
     //
     assert(MI->getOperand(0).isRegister() &&

diff --git a/lib/Target/X86/X86AsmPrinter.cpp b/lib/Target/X86/X86AsmPrinter.cpp
index 31ac00f7293740a72d98dbca29b7a651cf42c50e..f19b3422ae20d8d6e1e858a200bce6ba9822997e 100644 (file)
--- a/lib/Target/X86/X86AsmPrinter.cpp
+++ b/lib/Target/X86/X86AsmPrinter.cpp
@@ -665,7 +665,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
     // like: add r32, r/m32
     //
     // 3 Operands: in this form, we can have 'INST R1, R2, imm', which is used
-    // for instructions like the IMULri instructions.
+    // for instructions like the IMULrri instructions.
     //
     //
     assert(MI->getOperand(0).isRegister() &&

diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp
index ed61165b7e5f97f2036024a333d96aae0d161504..14089b9abb6f78989c57c5636fc606e765aa97f5 100644 (file)
--- a/lib/Target/X86/X86ISelSimple.cpp
+++ b/lib/Target/X86/X86ISelSimple.cpp
@@ -1524,10 +1524,10 @@ void ISel::doMultiplyConst(MachineBasicBlock *MBB,
   }
   
   if (Class == cShort) {
-    BMI(MBB, IP, X86::IMULri16, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
+    BMI(MBB, IP, X86::IMULrri16, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
     return;
   } else if (Class == cInt) {
-    BMI(MBB, IP, X86::IMULri32, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
+    BMI(MBB, IP, X86::IMULrri32, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
     return;
   }
 

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index f0206bab62420d96ef35fc7bfc1683b178b6dc72..0d72fcaceae0e331137851ae77f86ef0ff96ea7b 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -299,12 +299,20 @@ def SBBrr32  : I2A32<"sbb", 0x19, MRMDestReg>;                // R32 -= R32+Carr
 
 def IMULrr16 : I2A16<"imul", 0xAF, MRMSrcReg>, TB, OpSize, Pattern<(set R16, (times R16, R16))>;
 def IMULrr32 : I2A32<"imul", 0xAF, MRMSrcReg>, TB        , Pattern<(set R32, (times R32, R32))>;
+def IMULrm16 : I2A16<"imul", 0xAF, MRMSrcMem>, TB, OpSize;
+def IMULrm32 : I2A32<"imul", 0xAF, MRMSrcMem>, TB        ;
+
+
+// These are suprisingly enough not two address instructions!
+def IMULrri16  : X86Inst<"imul", 0x69, MRMSrcReg, Arg16>,     OpSize;  // R16 = R16*I16
+def IMULrri32  : X86Inst<"imul", 0x69, MRMSrcReg, Arg32>;              // R32 = R32*I32
+def IMULrri16b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8 >,     OpSize;  // R16 = R16*I8
+def IMULrri32b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8 >;              // R32 = R32*I8
+def IMULrmi16  : X86Inst<"imul", 0x69, MRMSrcMem, Arg16>,     OpSize;  // R16 = [mem16]*I16
+def IMULrmi32  : X86Inst<"imul", 0x69, MRMSrcMem, Arg32>;              // R32 = [mem32]*I32
+def IMULrmi16b : X86Inst<"imul", 0x6B, MRMSrcMem, Arg8 >,     OpSize;  // R16 = [mem16]*I8
+def IMULrmi32b : X86Inst<"imul", 0x6B, MRMSrcMem, Arg8 >;              // R32 = [mem32]*I8
 
-// These are suprisingly enough not two addres instructions!
-def IMULri16 : X86Inst<"imul", 0x69, MRMSrcReg, Arg16>,     OpSize;
-def IMULri32 : X86Inst<"imul", 0x69, MRMSrcReg, Arg32>;
-def IMULri16b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8>,     OpSize;
-def IMULri32b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8>;
 
 
 // Logical operators...

diff --git a/lib/Target/X86/X86PeepholeOpt.cpp b/lib/Target/X86/X86PeepholeOpt.cpp
index accbdd6dccb0e5d1cb9395be5609817f5d004506..512a72136693ca24ee1d59f6192fc3b5a845eccc 100644 (file)
--- a/lib/Target/X86/X86PeepholeOpt.cpp
+++ b/lib/Target/X86/X86PeepholeOpt.cpp
@@ -72,7 +72,7 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
     // immediate despite the fact that the operands are 16 or 32 bits.  Because
     // this can save three bytes of code size (and icache space), we want to
     // shrink them if possible.
-  case X86::IMULri16: case X86::IMULri32:
+  case X86::IMULrri16: case X86::IMULrri32:
     assert(MI->getNumOperands() == 3 && "These should all have 3 operands!");
     if (MI->getOperand(2).isImmediate()) {
       int Val = MI->getOperand(2).getImmedValue();
@@ -81,8 +81,8 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
         unsigned Opcode;
         switch (MI->getOpcode()) {
         default: assert(0 && "Unknown opcode value!");
-        case X86::IMULri16: Opcode = X86::IMULri16b; break;
-        case X86::IMULri32: Opcode = X86::IMULri32b; break;
+        case X86::IMULrri16: Opcode = X86::IMULrri16b; break;
+        case X86::IMULrri32: Opcode = X86::IMULrri32b; break;
         }
         unsigned R0 = MI->getOperand(0).getReg();
         unsigned R1 = MI->getOperand(1).getReg();
@@ -93,6 +93,31 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
     }
     return false;
 
+  case X86::IMULrmi16: case X86::IMULrmi32:
+    assert(MI->getNumOperands() == 6 && "These should all have 6 operands!");
+    if (MI->getOperand(5).isImmediate()) {
+      int Val = MI->getOperand(5).getImmedValue();
+      // If the value is the same when signed extended from 8 bits...
+      if (Val == (signed int)(signed char)Val) {
+        unsigned Opcode;
+        switch (MI->getOpcode()) {
+        default: assert(0 && "Unknown opcode value!");
+        case X86::IMULrmi16: Opcode = X86::IMULrmi16b; break;
+        case X86::IMULrmi32: Opcode = X86::IMULrmi32b; break;
+        }
+        unsigned R0 = MI->getOperand(0).getReg();
+        unsigned R1 = MI->getOperand(1).getReg();
+        unsigned Scale = MI->getOperand(2).getImmedValue();
+        unsigned R2 = MI->getOperand(3).getReg();
+        unsigned Offset = MI->getOperand(3).getImmedValue();
+        I = MBB.insert(MBB.erase(I),
+                       BuildMI(Opcode, 2, R0).addReg(R1).addZImm(Scale).
+                             addReg(R2).addSImm(Offset).addZImm((char)Val));
+        return true;
+      }
+    }
+    return false;
+
   case X86::ADDri16:  case X86::ADDri32:
   case X86::ADDmi16:  case X86::ADDmi32:
   case X86::SUBri16:  case X86::SUBri32: