UPSTREAM: phy: rockchip-dp: should be a child device of the GRF
authorJacob Chen <jacob2.chen@rock-chips.com>
Fri, 9 Dec 2016 06:40:51 +0000 (14:40 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Fri, 9 Dec 2016 10:14:14 +0000 (18:14 +0800)
The displayport-phy is fully enclosed in the general register files (GRF).
Therefore as seen from the device-tree it shouldn't be a separate platform-
device but instead a sub-device of the GRF - using the simply-mfd mechanism.

The driver entered the kernel in the current merge-window, so we can still
adapt the binding without needing a fallback, as the binding hasn't been
released with a full kernel yet.

While the edp phy is fully part of the GRF, it doesn't have any separate
register set there, so doesn't get any register-area assigned.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Change-Id: I44a857051be195386fc888b2c713bedc948d5c95
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
 (cherry picked from commit 0311c76e4722b8d6e5fa47eaee63c6552bcc74f5)

Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt [new file with mode: 0644]
drivers/phy/phy-rockchip-dp.c

diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
new file mode 100644 (file)
index 0000000..e3b4809
--- /dev/null
@@ -0,0 +1,26 @@
+Rockchip specific extensions to the Analogix Display Port PHY
+------------------------------------
+
+Required properties:
+- compatible : should be one of the following supported values:
+        - "rockchip.rk3288-dp-phy"
+- clocks: from common clock binding: handle to dp clock.
+       of memory mapped region.
+- clock-names: from common clock binding:
+       Required elements: "24m"
+- #phy-cells : from the generic PHY bindings, must be 0;
+
+Example:
+
+grf: syscon@ff770000 {
+       compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
+
+...
+
+       edp_phy: edp-phy {
+               compatible = "rockchip,rk3288-dp-phy";
+               clocks = <&cru SCLK_EDP_24M>;
+               clock-names = "24m";
+               #phy-cells = <0>;
+       };
+};
index 77e2d02e6bee228ac033a28cccea90047439ed86..793ecb6d87bcaa2a56a914b2745bea6453929637 100644 (file)
@@ -86,6 +86,9 @@ static int rockchip_dp_phy_probe(struct platform_device *pdev)
        if (!np)
                return -ENODEV;
 
+       if (!dev->parent || !dev->parent->of_node)
+               return -ENODEV;
+
        dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
        if (IS_ERR(dp))
                return -ENOMEM;
@@ -104,9 +107,9 @@ static int rockchip_dp_phy_probe(struct platform_device *pdev)
                return ret;
        }
 
-       dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+       dp->grf = syscon_node_to_regmap(dev->parent->of_node);
        if (IS_ERR(dp->grf)) {
-               dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
+               dev_err(dev, "rk3288-dp needs the General Register Files syscon\n");
                return PTR_ERR(dp->grf);
        }