clk: rockchip: rk3399: Add and export SCLK_RGA_CORE clock id
authorXing Zheng <zhengxing@rock-chips.com>
Tue, 19 Apr 2016 01:13:29 +0000 (09:13 +0800)
committerGerrit Code Review <gerrit@rock-chips.com>
Tue, 19 Apr 2016 02:27:18 +0000 (10:27 +0800)
Change-Id: Ia64289f565e7b4570c6b55810bda5d4711a7381a
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
drivers/clk/rockchip/clk-rk3399.c
include/dt-bindings/clock/rk3399-cru.h

index 7fbf48b15e5b788284cf1be8f2ea876b1837a7a0..2fb52744bcb29f2bf5b987fa1bcd4abd4d9df1bb 100644 (file)
@@ -771,7 +771,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                        RK3399_CLKGATE_CON(16), 1, GFLAGS),
 
        /* rga */
-       COMPOSITE(0, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
+       COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
                        RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3399_CLKGATE_CON(4), 10, GFLAGS),
 
index 10ce0a497cf2f1dac926d0e79a05316c598120d9..2290123f61e6d7d5c13f134735fc59c8463e4160 100644 (file)
@@ -72,7 +72,7 @@
 #define SCLK_MACREF_OUT                        106
 #define SCLK_VOP0_PWM                  107
 #define SCLK_VOP1_PWM                  108
-#define SCLK_RGA                       109
+#define SCLK_RGA_CORE                  109
 #define SCLK_ISP0                      110
 #define SCLK_ISP1                      111
 #define SCLK_HDMI_CEC                  112