#endif
board_mem_reserved();
}
-
+/******************************** arm dvfs frequency volt table **********************************/
/**
* dvfs_cpu_logic_table: table for arm and logic dvfs
* @frequency : arm frequency
* @cpu_volt : arm voltage depend on frequency
*/
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
+
+//sdk
+static struct cpufreq_frequency_table dvfs_arm_table_volt_level0[] = {
{.frequency = 312 * 1000, .index = 850 * 1000},
{.frequency = 504 * 1000, .index = 900 * 1000},
{.frequency = 816 * 1000, .index = 950 * 1000},
{.frequency = 1608 * 1000, .index = 1300 * 1000},
{.frequency = CPUFREQ_TABLE_END},
};
+//default
+static struct cpufreq_frequency_table dvfs_arm_table_volt_level1[] = {
+ {.frequency = 312 * 1000, .index = 875 * 1000},
+ {.frequency = 504 * 1000, .index = 925 * 1000},
+ {.frequency = 816 * 1000, .index = 975 * 1000},
+ {.frequency = 1008 * 1000, .index = 1075 * 1000},
+ {.frequency = 1200 * 1000, .index = 1150 * 1000},
+ {.frequency = 1416 * 1000, .index = 1250 * 1000},
+ {.frequency = 1608 * 1000, .index = 1350 * 1000},
+ {.frequency = CPUFREQ_TABLE_END},
+};
+// cube 10'
+static struct cpufreq_frequency_table dvfs_arm_table_volt_level2[] = {
+ {.frequency = 312 * 1000, .index = 900 * 1000},
+ {.frequency = 504 * 1000, .index = 925 * 1000},
+ {.frequency = 816 * 1000, .index = 1000 * 1000},
+ {.frequency = 1008 * 1000, .index = 1075 * 1000},
+ {.frequency = 1200 * 1000, .index = 1200 * 1000},
+ {.frequency = 1416 * 1000, .index = 1250 * 1000},
+ {.frequency = 1608 * 1000, .index = 1350 * 1000},
+ {.frequency = CPUFREQ_TABLE_END},
+};
+//if you board is good for volt quality,select dvfs_arm_table_volt_level0
+#define dvfs_arm_table dvfs_arm_table_volt_level1
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
+/******************************** gpu dvfs frequency volt table **********************************/
+//sdk
+static struct cpufreq_frequency_table dvfs_gpu_table_volt_level0[] = {
#if defined(CONFIG_ARCH_RK3188)
{.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
#elif defined(CONFIG_ARCH_RK3066B)
{.frequency = 600 * 1000, .index = 1200 * 1000},
{.frequency = CPUFREQ_TABLE_END},
};
+//cube 10'
+static struct cpufreq_frequency_table dvfs_gpu_table_volt_level1[] = {
+#if defined(CONFIG_ARCH_RK3188)
+ {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
+#elif defined(CONFIG_ARCH_RK3066B)
+ {.frequency = 100 * 1000, .index = 950 * 1000},//the minimum rate is no limit for rk3168 rk3066B
+#endif
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
+ {.frequency = 200 * 1000, .index = 1000 * 1000},
+ {.frequency = 266 * 1000, .index = 1025 * 1000},
+ {.frequency = 300 * 1000, .index = 1050 * 1000},
+ {.frequency = 400 * 1000, .index = 1100 * 1000},
+ {.frequency = 600 * 1000, .index = 1250 * 1000},
+ {.frequency = CPUFREQ_TABLE_END},
+};
+
+#define dvfs_gpu_table dvfs_gpu_table_volt_level1
+
+/******************************** ddr dvfs frequency volt table **********************************/
+static struct cpufreq_frequency_table dvfs_ddr_table_volt_level0[] = {
#if defined(CONFIG_ARCH_RK3188)
{.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
{.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1000 * 1000},
#endif
{.frequency = 396 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
+ //{.frequency = 528 * 1000 + DDR_FREQ_NORMAL, .index = 1200 * 1000},
{.frequency = CPUFREQ_TABLE_END},
};
+#define dvfs_ddr_table dvfs_ddr_table_volt_level0
+
+/******************************** arm dvfs frequency volt table end **********************************/
+
+
+
//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];