drm/i915: Include display_mmio_offset in sequencer index/data registers
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 25 Jan 2013 19:44:45 +0000 (21:44 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Sat, 26 Jan 2013 16:32:03 +0000 (17:32 +0100)
SR01 needs to be touched to disable VGA on non-UMS setups too.
So the sequencer registers need to include the appripriate offset
on VLV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h

index 452cb18818dc9b61624a61c7cae9b13651a41e7a..5944b4b690316983ac38eaea74dbe3ad1de43e32 100644 (file)
 #define   VGA_MSR_MEM_EN (1<<1)
 #define   VGA_MSR_CGA_MODE (1<<0)
 
-#define VGA_SR_INDEX 0x3c4
+/*
+ * SR01 is the only VGA register touched on non-UMS setups.
+ * VLV doesn't do UMS, so the sequencer index/data registers
+ * are the only VGA registers which need to include
+ * display_mmio_offset.
+ */
+#define VGA_SR_INDEX (dev_priv->info->display_mmio_offset + 0x3c4)
 #define SR01                   1
-#define VGA_SR_DATA 0x3c5
+#define VGA_SR_DATA (dev_priv->info->display_mmio_offset + 0x3c5)
 
 #define VGA_AR_INDEX 0x3c0
 #define   VGA_AR_VID_EN (1<<5)