#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
+/* some boards require extra gpio capacity to support external
+ * devices that need GPIO.
+ */
+
+#define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA)
+
#include <asm-generic/gpio.h>
s3c2412_clkcon_enable(clkp, 0);
}
+ s3c_pwmclk_init();
return 0;
}
.bus_num = 1,
.pin_clk = S3C2410_GPG8,
.pin_mosi = S3C2410_GPB8,
+ .num_chipselect = 1,
.chip_select = jive_lcd_spi_chipselect,
};
static struct platform_device jive_device_lcdspi = {
- .name = "s3c24xx-spi-gpio",
+ .name = "spi_s3c24xx_gpio",
.id = 1,
.num_resources = 0,
.dev.platform_data = &jive_lcd_spi,
.bus_num = 2,
.pin_clk = S3C2410_GPB4,
.pin_mosi = S3C2410_GPB9,
+ .num_chipselect = 1,
.chip_select = jive_wm8750_chipselect,
};
static struct platform_device jive_device_wm8750 = {
- .name = "s3c24xx-spi-gpio",
+ .name = "spi_s3c24xx_gpio",
.id = 2,
.num_resources = 0,
.dev.platform_data = &jive_wm8750_spi,
select S3C24XX_DCLK
select PM_SIMTEC if PM
select HAVE_PATA_PLATFORM
+ select S3C24XX_GPIO_EXTRA64
help
Say Y here if you are using the Simtec Electronics ANUBIS
development system
select CPU_S3C2440
select S3C24XX_DCLK
select PM_SIMTEC if PM
+ select S3C24XX_GPIO_EXTRA128
help
Say Y here if you are using the Simtec IM2440D20 module, also
known as the Osiris.
.mask = 0,
},
+ .devices = SM501_USE_GPIO,
+
/* set the SDRAM and bus clocks */
.mclk = 72 * MHZ,
.m1xclk = 144 * MHZ,
static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
[0] = {
+ .bus_num = 1,
.pin_scl = 44,
.pin_sda = 45,
},
[1] = {
+ .bus_num = 2,
.pin_scl = 40,
.pin_sda = 41,
},
static struct sm501_platdata anubis_sm501_platdata = {
.init = &anubis_sm501_initdata,
+ .gpio_base = -1,
.gpio_i2c = anubis_sm501_gpio_i2c,
.gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c),
};
#include <asm/mach/irq.h>
#include <mach/hardware.h>
+#include <mach/fb.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
+#include <asm/plat-s3c24xx/mci.h>
static struct map_desc at2440evb_iodesc[] __initdata = {
/* Nothing here */
},
};
+static struct s3c24xx_mci_pdata at2440evb_mci_pdata = {
+ .gpio_detect = S3C2410_GPG10,
+};
+
+/* 7" LCD panel */
+
+static struct s3c2410fb_display at2440evb_lcd_cfg __initdata = {
+
+ .lcdcon5 = S3C2410_LCDCON5_FRM565 |
+ S3C2410_LCDCON5_INVVLINE |
+ S3C2410_LCDCON5_INVVFRAME |
+ S3C2410_LCDCON5_PWREN |
+ S3C2410_LCDCON5_HWSWP,
+
+ .type = S3C2410_LCDCON1_TFT,
+
+ .width = 800,
+ .height = 480,
+
+ .pixclock = 33333, /* HCLK 60 MHz, divisor 2 */
+ .xres = 800,
+ .yres = 480,
+ .bpp = 16,
+ .left_margin = 88,
+ .right_margin = 40,
+ .hsync_len = 128,
+ .upper_margin = 32,
+ .lower_margin = 11,
+ .vsync_len = 2,
+};
+
+static struct s3c2410fb_mach_info at2440evb_fb_info __initdata = {
+ .displays = &at2440evb_lcd_cfg,
+ .num_displays = 1,
+ .default_display = 0,
+};
+
static struct platform_device *at2440evb_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_wdt,
&s3c_device_i2c0,
&s3c_device_rtc,
&s3c_device_nand,
+ &s3c_device_sdi,
+ &s3c_device_lcd,
&at2440evb_device_eth,
};
static void __init at2440evb_map_io(void)
{
s3c_device_nand.dev.platform_data = &at2440evb_nand_info;
+ s3c_device_sdi.name = "s3c2440-sdi";
+ s3c_device_sdi.dev.platform_data = &at2440evb_mci_pdata;
s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
s3c24xx_init_clocks(16934400);
static void __init at2440evb_init(void)
{
+ s3c24xx_fb_set_platdata(&at2440evb_fb_info);
s3c_i2c0_set_platdata(NULL);
+
platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
}
(clkp->enable)(clkp, 0);
}
+
+ s3c_pwmclk_init();
}
--- /dev/null
+/* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64xx - pwm clock and timer support
+ */
+
+/**
+ * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
+ * @tcfg: The timer TCFG1 register bits shifted down to 0.
+ *
+ * Return true if the given configuration from TCFG1 is a TCLK instead
+ * any of the TDIV clocks.
+ */
+static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
+{
+ return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
+}
+
+/**
+ * tcfg_to_divisor() - convert tcfg1 setting to a divisor
+ * @tcfg1: The tcfg1 setting, shifted down.
+ *
+ * Get the divisor value for the given tcfg1 setting. We assume the
+ * caller has already checked to see if this is not a TCLK source.
+ */
+static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
+{
+ return 1 << tcfg1;
+}
+
+/**
+ * pwm_tdiv_has_div1() - does the tdiv setting have a /1
+ *
+ * Return true if we have a /1 in the tdiv setting.
+ */
+static inline unsigned int pwm_tdiv_has_div1(void)
+{
+ return 1;
+}
+
+/**
+ * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
+ * @div: The divisor to calculate the bit information for.
+ *
+ * Turn a divisor into the necessary bit field for TCFG1.
+ */
+static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
+{
+ return ilog2(div);
+}
+
+#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
static void arch_detect_cpu(void)
{
/* we do not need to do any cpu detection here at the moment. */
+ fifo_mask = S3C2440_UFSTAT_TXMASK;
+ fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
}
#endif /* __ASM_ARCH_UNCOMPRESS_H */
{ I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
};
-extern void s3c64xx_init_io(struct map_desc *, int);
-
static void __init smdk6410_map_io(void)
{
s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
Say y here to use the watchdog to reset the system if the
kernel decompressor detects an error during decompression.
+config S3C_BOOT_UART_FORCE_FIFO
+ bool "Force UART FIFO on during boot process"
+ depends on PLAT_S3C
+ default y
+ help
+ Say Y here to force the UART FIFOs on during the kernel
+ uncompressor
+
comment "Power management"
config S3C2410_PM_DEBUG
--- /dev/null
+/* arch/arm/plat-s3c/include/plat/adc.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ * http://armlinux.simnte.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX ADC driver information
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_ADC_H
+#define __ASM_PLAT_ADC_H __FILE__
+
+struct s3c_adc_client;
+
+extern int s3c_adc_start(struct s3c_adc_client *client,
+ unsigned int channel, unsigned int nr_samples);
+
+extern struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
+ void (*select)(unsigned selected),
+ void (*conv)(unsigned d0, unsigned d1),
+ unsigned int is_ts);
+
+extern void s3c_adc_release(struct s3c_adc_client *client);
+
+#endif /* __ASM_PLAT_ADC_H */
/* S3C64XX specific functions and clocks */
extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
+
+/* Init for pwm clock code */
+
+extern void s3c_pwmclk_init(void);
+
extern void s3c64xx_init_irq(u32 vic0, u32 vic1);
extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
+extern void s3c64xx_init_io(struct map_desc *mach_desc, int size);
extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
#define S3C2410_TCFG1_MUX_TCLK (4<<0)
#define S3C2410_TCFG1_MUX_MASK (15<<0)
+#define S3C64XX_TCFG1_MUX_DIV1 (0<<0)
+#define S3C64XX_TCFG1_MUX_DIV2 (1<<0)
+#define S3C64XX_TCFG1_MUX_DIV4 (2<<0)
+#define S3C64XX_TCFG1_MUX_DIV8 (3<<0)
+#define S3C64XX_TCFG1_MUX_DIV16 (4<<0)
+#define S3C64XX_TCFG1_MUX_TCLK (5<<0) /* 3 sets of TCLK */
+#define S3C64XX_TCFG1_MUX_MASK (15<<0)
+
#define S3C2410_TCFG1_SHIFT(x) ((x) * 4)
/* for each timer, we have an count buffer, an compare buffer and
static void error(char *err);
+#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
+static inline void arch_enable_uart_fifo(void)
+{
+ u32 fifocon = uart_rd(S3C2410_UFCON);
+
+ if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
+ fifocon |= S3C2410_UFCON_RESETBOTH;
+ uart_wr(S3C2410_UFCON, fifocon);
+
+ /* wait for fifo reset to complete */
+ while (1) {
+ fifocon = uart_rd(S3C2410_UFCON);
+ if (!(fifocon & S3C2410_UFCON_RESETBOTH))
+ break;
+ }
+ }
+}
+#else
+#define arch_enable_uart_fifo() do { } while(0)
+#endif
+
+
static void
arch_decomp_setup(void)
{
arch_detect_cpu();
arch_decomp_wdog_start();
+
+ /* Enable the UART FIFOs if they where not enabled and our
+ * configuration says we should turn them on.
+ */
+
+ arch_enable_uart_fifo();
}
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
+#include <linux/log2.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <plat/cpu.h>
#include <plat/regs-timer.h>
+#include <mach/pwm-clock.h>
/* Each of the timers 0 through 5 go through the following
* clock tree, with the inputs depending on the timers.
return container_of(clk, struct pwm_tdiv_clk, clk);
}
-static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
-{
- return 1 << (1 + tcfg1);
-}
-
static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
{
unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
tcfg1 &= S3C2410_TCFG1_MUX_MASK;
- if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)
+ if (pwm_cfg_src_is_tclk(tcfg1))
divisor = to_tdiv(clk)->divisor;
else
divisor = tcfg_to_divisor(tcfg1);
parent_rate = clk_get_rate(clk->parent);
divisor = parent_rate / rate;
- if (divisor <= 2)
+ if (divisor <= 1 && pwm_tdiv_has_div1())
+ divisor = 1;
+ else if (divisor <= 2)
divisor = 2;
else if (divisor <= 4)
divisor = 4;
static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
{
- unsigned long bits;
-
- switch (divclk->divisor) {
- case 2:
- bits = S3C2410_TCFG1_MUX_DIV2;
- break;
- case 4:
- bits = S3C2410_TCFG1_MUX_DIV4;
- break;
- case 8:
- bits = S3C2410_TCFG1_MUX_DIV8;
- break;
- case 16:
- default:
- bits = S3C2410_TCFG1_MUX_DIV16;
- break;
- }
-
- return bits;
+ return pwm_tdiv_div_bits(divclk->divisor);
}
static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
/* Update the current MUX settings if we are currently
* selected as the clock source for this clock. */
- if (tcfg1 != S3C2410_TCFG1_MUX_TCLK)
+ if (!pwm_cfg_src_is_tclk(tcfg1))
clk_pwm_tdiv_update(divclk);
return 0;
unsigned long shift = S3C2410_TCFG1_SHIFT(id);
if (parent == s3c24xx_pwmclk_tclk(id))
- bits = S3C2410_TCFG1_MUX_TCLK << shift;
+ bits = S3C_TCFG1_MUX_TCLK << shift;
else if (parent == s3c24xx_pwmclk_tdiv(id))
bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
else
tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
tcfg1 &= S3C2410_TCFG1_MUX_MASK;
- if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)
+ if (pwm_cfg_src_is_tclk(tcfg1))
parent = s3c24xx_pwmclk_tclk(id);
else
parent = s3c24xx_pwmclk_tdiv(id);
return clk_set_parent(pwm, parent);
}
-static __init int s3c24xx_pwmclk_init(void)
+/**
+ * s3c_pwmclk_init() - initialise pwm clocks
+ *
+ * Initialise and register the clocks which provide the inputs for the
+ * pwm timer blocks.
+ *
+ * Note, this call is required by the time core, so must be called after
+ * the base clocks are added and before any of the initcalls are run.
+ */
+__init void s3c_pwmclk_init(void)
{
struct clk *clk_timers;
unsigned int clk;
clk_timers = clk_get(NULL, "timers");
if (IS_ERR(clk_timers)) {
printk(KERN_ERR "%s: no parent clock\n", __func__);
- return -EINVAL;
+ return;
}
for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) {
ret = s3c24xx_register_clock(&clk_timer_scaler[clk]);
if (ret < 0) {
printk(KERN_ERR "error adding pwm scaler%d clock\n", clk);
- goto err;
+ return;
}
}
ret = s3c24xx_register_clock(&clk_timer_tclk[clk]);
if (ret < 0) {
printk(KERN_ERR "error adding pww tclk%d\n", clk);
- goto err;
+ return;
}
}
ret = clk_pwm_tdiv_register(clk);
if (ret < 0) {
printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
- goto err;
+ return;
}
}
ret = clk_pwm_tin_register(&clk_tin[clk]);
if (ret < 0) {
printk(KERN_ERR "error adding pwm%d tin clock\n", clk);
- goto err;
+ return;
}
}
-
- return 0;
-
- err:
- return ret;
}
-
-arch_initcall(s3c24xx_pwmclk_init);
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/platform_device.h>
#include <asm/system.h>
#include <asm/leds.h>
machine_is_anubis() || \
machine_is_osiris())
+static struct clk *tin;
+static struct clk *tdiv;
+static struct clk *timerclk;
+
/*
* Set up timer interrupt, and return the current time in seconds.
*
tcnt = TICK_MAX; /* default value for tcnt */
- /* read the current timer configuration bits */
-
- tcon = __raw_readl(S3C2410_TCON);
- tcfg1 = __raw_readl(S3C2410_TCFG1);
- tcfg0 = __raw_readl(S3C2410_TCFG0);
-
/* configure the system for whichever machine is in use */
if (use_tclk1_12()) {
timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
tcnt = 12000000 / HZ;
+ tcfg1 = __raw_readl(S3C2410_TCFG1);
tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
+ __raw_writel(tcfg1, S3C2410_TCFG1);
} else {
unsigned long pclk;
- struct clk *clk;
+ struct clk *tscaler;
/* for the h1940 (and others), we use the pclk from the core
* to generate the timer values. since values around 50 to
* (8.45 ticks per usec)
*/
- /* this is used as default if no other timer can be found */
-
- clk = clk_get(NULL, "timers");
- if (IS_ERR(clk))
- panic("failed to get clock for system timer");
-
- clk_enable(clk);
-
- pclk = clk_get_rate(clk);
+ pclk = clk_get_rate(timerclk);
/* configure clock tick */
timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
- tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
- tcfg1 |= S3C2410_TCFG1_MUX4_DIV2;
+ tscaler = clk_get_parent(tdiv);
- tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
- tcfg0 |= ((6 - 1) / 2) << S3C2410_TCFG_PRESCALER1_SHIFT;
+ clk_set_rate(tscaler, pclk / 3);
+ clk_set_rate(tdiv, pclk / 6);
+ clk_set_parent(tin, tdiv);
- tcnt = (pclk / 6) / HZ;
+ tcnt = clk_get_rate(tin) / HZ;
}
+ tcon = __raw_readl(S3C2410_TCON);
+ tcfg0 = __raw_readl(S3C2410_TCFG0);
+ tcfg1 = __raw_readl(S3C2410_TCFG1);
+
/* timers reload after counting zero, so reduce the count by 1 */
tcnt--;
__raw_writel(tcon, S3C2410_TCON);
}
+static void __init s3c2410_timer_resources(void)
+{
+ struct platform_device tmpdev;
+
+ tmpdev.dev.bus = &platform_bus_type;
+ tmpdev.id = 4;
+
+ timerclk = clk_get(NULL, "timers");
+ if (IS_ERR(timerclk))
+ panic("failed to get clock for system timer");
+
+ clk_enable(timerclk);
+
+ if (!use_tclk1_12()) {
+ tin = clk_get(&tmpdev.dev, "pwm-tin");
+ if (IS_ERR(tin))
+ panic("failed to get pwm-tin clock for system timer");
+
+ tdiv = clk_get(&tmpdev.dev, "pwm-tdiv");
+ if (IS_ERR(tdiv))
+ panic("failed to get pwm-tdiv clock for system timer");
+ }
+
+ clk_enable(tin);
+}
+
static void __init s3c2410_timer_init(void)
{
+ s3c2410_timer_resources();
s3c2410_timer_setup();
setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
}
Support for exporting the PWM timer blocks via the pwm device
system.
+
+# gpio configurations
+
+config S3C24XX_GPIO_EXTRA
+ int
+ default 128 if S3C24XX_GPIO_EXTRA128
+ default 64 if S3C24XX_GPIO_EXTRA64
+ default 0
+
+config S3C24XX_GPIO_EXTRA64
+ bool
+ help
+ Add an extra 64 gpio numbers to the available GPIO pool. This is
+ available for boards that need extra gpios for external devices.
+
+config S3C24XX_GPIO_EXTRA128
+ bool
+ help
+ Add an extra 128 gpio numbers to the available GPIO pool. This is
+ available for boards that need extra gpios for external devices.
+
config PM_SIMTEC
bool
help
Enable debugging output for the DMA code. This option sends info
to the kernel log, at priority KERN_DEBUG.
+config S3C24XX_ADC
+ bool "ADC common driver support"
+ help
+ Core support for the ADC block found in the S3C24XX SoC systems
+ for drivers such as the touchscreen and hwmon to use to share
+ this resource.
+
# SPI default pin configuration code
config S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13
obj-$(CONFIG_HAVE_PWM) += pwm.o
obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o
obj-$(CONFIG_S3C2410_DMA) += dma.o
+obj-$(CONFIG_S3C24XX_ADC) += adc.o
# device specific setup and/or initialisation
obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o
--- /dev/null
+/* arch/arm/plat-s3c24xx/adc.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
+ *
+ * S3C24XX ADC device core
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/list.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+
+#include <plat/regs-adc.h>
+#include <plat/adc.h>
+
+/* This driver is designed to control the usage of the ADC block between
+ * the touchscreen and any other drivers that may need to use it, such as
+ * the hwmon driver.
+ *
+ * Priority will be given to the touchscreen driver, but as this itself is
+ * rate limited it should not starve other requests which are processed in
+ * order that they are received.
+ *
+ * Each user registers to get a client block which uniquely identifies it
+ * and stores information such as the necessary functions to callback when
+ * action is required.
+ */
+
+struct s3c_adc_client {
+ struct platform_device *pdev;
+ struct list_head pend;
+
+ unsigned int nr_samples;
+ unsigned char is_ts;
+ unsigned char channel;
+
+ void (*select_cb)(unsigned selected);
+ void (*convert_cb)(unsigned val1, unsigned val2);
+};
+
+struct adc_device {
+ struct platform_device *pdev;
+ struct platform_device *owner;
+ struct clk *clk;
+ struct s3c_adc_client *cur;
+ struct s3c_adc_client *ts_pend;
+ void __iomem *regs;
+
+ unsigned int prescale;
+
+ int irq;
+};
+
+static struct adc_device *adc_dev;
+
+static LIST_HEAD(adc_pending);
+
+#define adc_dbg(_adc, msg...) dev_dbg(&(_adc)->pdev->dev, msg)
+
+static inline void s3c_adc_convert(struct adc_device *adc)
+{
+ unsigned con = readl(adc->regs + S3C2410_ADCCON);
+
+ con |= S3C2410_ADCCON_ENABLE_START;
+ writel(con, adc->regs + S3C2410_ADCCON);
+}
+
+static inline void s3c_adc_select(struct adc_device *adc,
+ struct s3c_adc_client *client)
+{
+ unsigned con = readl(adc->regs + S3C2410_ADCCON);
+
+ client->select_cb(1);
+
+ con &= ~S3C2410_ADCCON_MUXMASK;
+ con &= ~S3C2410_ADCCON_STDBM;
+ con &= ~S3C2410_ADCCON_STARTMASK;
+
+ if (!client->is_ts)
+ con |= S3C2410_ADCCON_SELMUX(client->channel);
+
+ writel(con, adc->regs + S3C2410_ADCCON);
+}
+
+static void s3c_adc_dbgshow(struct adc_device *adc)
+{
+ adc_dbg(adc, "CON=%08x, TSC=%08x, DLY=%08x\n",
+ readl(adc->regs + S3C2410_ADCCON),
+ readl(adc->regs + S3C2410_ADCTSC),
+ readl(adc->regs + S3C2410_ADCDLY));
+}
+
+void s3c_adc_try(struct adc_device *adc)
+{
+ struct s3c_adc_client *next = adc->ts_pend;
+
+ if (!next && !list_empty(&adc_pending)) {
+ next = list_first_entry(&adc_pending,
+ struct s3c_adc_client, pend);
+ list_del(&next->pend);
+ } else
+ adc->ts_pend = NULL;
+
+ if (next) {
+ adc_dbg(adc, "new client is %p\n", next);
+ adc->cur = next;
+ s3c_adc_select(adc, next);
+ s3c_adc_convert(adc);
+ s3c_adc_dbgshow(adc);
+ }
+}
+
+int s3c_adc_start(struct s3c_adc_client *client,
+ unsigned int channel, unsigned int nr_samples)
+{
+ struct adc_device *adc = adc_dev;
+ unsigned long flags;
+
+ if (!adc) {
+ printk(KERN_ERR "%s: failed to find adc\n", __func__);
+ return -EINVAL;
+ }
+
+ if (client->is_ts && adc->ts_pend)
+ return -EAGAIN;
+
+ local_irq_save(flags);
+
+ client->channel = channel;
+ client->nr_samples = nr_samples;
+
+ if (client->is_ts)
+ adc->ts_pend = client;
+ else
+ list_add_tail(&client->pend, &adc_pending);
+
+ if (!adc->cur)
+ s3c_adc_try(adc);
+ local_irq_restore(flags);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(s3c_adc_start);
+
+static void s3c_adc_default_select(unsigned select)
+{
+}
+
+struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
+ void (*select)(unsigned int selected),
+ void (*conv)(unsigned d0, unsigned d1),
+ unsigned int is_ts)
+{
+ struct s3c_adc_client *client;
+
+ WARN_ON(!pdev);
+ WARN_ON(!conv);
+
+ if (!select)
+ select = s3c_adc_default_select;
+
+ if (!conv || !pdev)
+ return ERR_PTR(-EINVAL);
+
+ client = kzalloc(sizeof(struct s3c_adc_client), GFP_KERNEL);
+ if (!client) {
+ dev_err(&pdev->dev, "no memory for adc client\n");
+ return ERR_PTR(-ENOMEM);
+ }
+
+ client->pdev = pdev;
+ client->is_ts = is_ts;
+ client->select_cb = select;
+ client->convert_cb = conv;
+
+ return client;
+}
+EXPORT_SYMBOL_GPL(s3c_adc_register);
+
+void s3c_adc_release(struct s3c_adc_client *client)
+{
+ /* We should really check that nothing is in progress. */
+ kfree(client);
+}
+EXPORT_SYMBOL_GPL(s3c_adc_release);
+
+static irqreturn_t s3c_adc_irq(int irq, void *pw)
+{
+ struct adc_device *adc = pw;
+ struct s3c_adc_client *client = adc->cur;
+ unsigned long flags;
+ unsigned data0, data1;
+
+ if (!client) {
+ dev_warn(&adc->pdev->dev, "%s: no adc pending\n", __func__);
+ return IRQ_HANDLED;
+ }
+
+ data0 = readl(adc->regs + S3C2410_ADCDAT0);
+ data1 = readl(adc->regs + S3C2410_ADCDAT1);
+ adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1);
+
+ (client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff);
+
+ if (--client->nr_samples > 0) {
+ /* fire another conversion for this */
+
+ client->select_cb(1);
+ s3c_adc_convert(adc);
+ } else {
+ local_irq_save(flags);
+ (client->select_cb)(0);
+ adc->cur = NULL;
+
+ s3c_adc_try(adc);
+ local_irq_restore(flags);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int s3c_adc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct adc_device *adc;
+ struct resource *regs;
+ int ret;
+
+ adc = kzalloc(sizeof(struct adc_device), GFP_KERNEL);
+ if (adc == NULL) {
+ dev_err(dev, "failed to allocate adc_device\n");
+ return -ENOMEM;
+ }
+
+ adc->pdev = pdev;
+ adc->prescale = S3C2410_ADCCON_PRSCVL(49);
+
+ adc->irq = platform_get_irq(pdev, 1);
+ if (adc->irq <= 0) {
+ dev_err(dev, "failed to get adc irq\n");
+ ret = -ENOENT;
+ goto err_alloc;
+ }
+
+ ret = request_irq(adc->irq, s3c_adc_irq, 0, dev_name(dev), adc);
+ if (ret < 0) {
+ dev_err(dev, "failed to attach adc irq\n");
+ goto err_alloc;
+ }
+
+ adc->clk = clk_get(dev, "adc");
+ if (IS_ERR(adc->clk)) {
+ dev_err(dev, "failed to get adc clock\n");
+ ret = PTR_ERR(adc->clk);
+ goto err_irq;
+ }
+
+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!regs) {
+ dev_err(dev, "failed to find registers\n");
+ ret = -ENXIO;
+ goto err_clk;
+ }
+
+ adc->regs = ioremap(regs->start, resource_size(regs));
+ if (!adc->regs) {
+ dev_err(dev, "failed to map registers\n");
+ ret = -ENXIO;
+ goto err_clk;
+ }
+
+ clk_enable(adc->clk);
+
+ writel(adc->prescale | S3C2410_ADCCON_PRSCEN,
+ adc->regs + S3C2410_ADCCON);
+
+ dev_info(dev, "attached adc driver\n");
+
+ platform_set_drvdata(pdev, adc);
+ adc_dev = adc;
+
+ return 0;
+
+ err_clk:
+ clk_put(adc->clk);
+
+ err_irq:
+ free_irq(adc->irq, adc);
+
+ err_alloc:
+ kfree(adc);
+ return ret;
+}
+
+static int s3c_adc_remove(struct platform_device *pdev)
+{
+ struct adc_device *adc = platform_get_drvdata(pdev);
+
+ iounmap(adc->regs);
+ free_irq(adc->irq, adc);
+ clk_disable(adc->clk);
+ clk_put(adc->clk);
+ kfree(adc);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct adc_device *adc = platform_get_drvdata(pdev);
+ u32 con;
+
+ con = readl(adc->regs + S3C2410_ADCCON);
+ con |= S3C2410_ADCCON_STDBM;
+ writel(con, adc->regs + S3C2410_ADCCON);
+
+ clk_disable(adc->clk);
+
+ return 0;
+}
+
+static int s3c_adc_resume(struct platform_device *pdev)
+{
+ struct adc_device *adc = platform_get_drvdata(pdev);
+
+ clk_enable(adc->clk);
+
+ writel(adc->prescale | S3C2410_ADCCON_PRSCEN,
+ adc->regs + S3C2410_ADCCON);
+
+ return 0;
+}
+
+#else
+#define s3c_adc_suspend NULL
+#define s3c_adc_resume NULL
+#endif
+
+static struct platform_driver s3c_adc_driver = {
+ .driver = {
+ .name = "s3c24xx-adc",
+ .owner = THIS_MODULE,
+ },
+ .probe = s3c_adc_probe,
+ .remove = __devexit_p(s3c_adc_remove),
+ .suspend = s3c_adc_suspend,
+ .resume = s3c_adc_resume,
+};
+
+static int __init adc_init(void)
+{
+ int ret;
+
+ ret = platform_driver_register(&s3c_adc_driver);
+ if (ret)
+ printk(KERN_ERR "%s: failed to add adc driver\n", __func__);
+
+ return ret;
+}
+
+arch_initcall(adc_init);
};
struct platform_device s3c_device_adc = {
- .name = "s3c2410-adc",
+ .name = "s3c24xx-adc",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_adc_resource),
.resource = s3c_adc_resource,
};
+/* HWMON */
+
+struct platform_device s3c_device_hwmon = {
+ .name = "s3c24xx-hwmon",
+ .id = -1,
+ .dev.parent = &s3c_device_adc.dev,
+};
+
/* SDI */
static struct resource s3c_sdi_resource[] = {
--- /dev/null
+/* linux/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
+ *
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C24xx - pwm clock and timer support
+ */
+
+/**
+ * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
+ * @cfg: The timer TCFG1 register bits shifted down to 0.
+ *
+ * Return true if the given configuration from TCFG1 is a TCLK instead
+ * any of the TDIV clocks.
+ */
+static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
+{
+ return tcfg == S3C2410_TCFG1_MUX_TCLK;
+}
+
+/**
+ * tcfg_to_divisor() - convert tcfg1 setting to a divisor
+ * @tcfg1: The tcfg1 setting, shifted down.
+ *
+ * Get the divisor value for the given tcfg1 setting. We assume the
+ * caller has already checked to see if this is not a TCLK source.
+ */
+static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
+{
+ return 1 << (1 + tcfg1);
+}
+
+/**
+ * pwm_tdiv_has_div1() - does the tdiv setting have a /1
+ *
+ * Return true if we have a /1 in the tdiv setting.
+ */
+static inline unsigned int pwm_tdiv_has_div1(void)
+{
+ return 0;
+}
+
+/**
+ * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
+ * @div: The divisor to calculate the bit information for.
+ *
+ * Turn a divisor into the necessary bit field for TCFG1.
+ */
+static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
+{
+ return ilog2(div) - 1;
+}
+
+#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK
(clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
(clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
+ s3c_pwmclk_init();
return 0;
}
#include <mach/hardware.h>
#include <mach/map.h>
+#include <plat/regs-sys.h>
#include <plat/regs-clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
.rate = 27000000,
};
+static int clk_48m_ctrl(struct clk *clk, int enable)
+{
+ unsigned long flags;
+ u32 val;
+
+ /* can't rely on clock lock, this register has other usages */
+ local_irq_save(flags);
+
+ val = __raw_readl(S3C64XX_OTHERS);
+ if (enable)
+ val |= S3C64XX_OTHERS_USBMASK;
+ else
+ val &= ~S3C64XX_OTHERS_USBMASK;
+
+ __raw_writel(val, S3C64XX_OTHERS);
+ local_irq_restore(flags);
+
+ return 0;
+}
+
struct clk clk_48m = {
.name = "clk_48m",
.id = -1,
.rate = 48000000,
+ .enable = clk_48m_ctrl,
};
static int inline s3c64xx_gate(void __iomem *reg,
(clkp->enable)(clkp, 0);
}
+
+ s3c_pwmclk_init();
}
* published by the Free Software Foundation.
*/
-#define S3C6400_PLL_MDIV_MASK ((1 << (25-16)) - 1)
-#define S3C6400_PLL_PDIV_MASK ((1 << (13-8)) - 1)
-#define S3C6400_PLL_SDIV_MASK ((1 << (2-0)) - 1)
+#define S3C6400_PLL_MDIV_MASK ((1 << (25-16+1)) - 1)
+#define S3C6400_PLL_PDIV_MASK ((1 << (13-8+1)) - 1)
+#define S3C6400_PLL_SDIV_MASK ((1 << (2-0+1)) - 1)
#define S3C6400_PLL_MDIV_SHIFT (16)
#define S3C6400_PLL_PDIV_SHIFT (8)
#define S3C6400_PLL_SDIV_SHIFT (0)
#define S3C6400_CLKSRC_MMC2_SHIFT (22)
#define S3C6400_CLKSRC_MMC1_MASK (0x3 << 20)
#define S3C6400_CLKSRC_MMC1_SHIFT (20)
-#define S3C6400_CLKSRC_MMC0_MASK (0xf << 1)
-#define S3C6400_CLKSRC_MMC0_SHIFT (1)
+#define S3C6400_CLKSRC_MMC0_MASK (0x3 << 18)
+#define S3C6400_CLKSRC_MMC0_SHIFT (18)
#define S3C6400_CLKSRC_SPI1_MASK (0x3 << 16)
#define S3C6400_CLKSRC_SPI1_SHIFT (16)
#define S3C6400_CLKSRC_SPI0_MASK (0x3 << 14)
--- /dev/null
+/* arch/arm/plat-s3c64xx/include/plat/regs-sys.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX system register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_REGS_SYS_H
+#define __PLAT_REGS_SYS_H __FILE__
+
+#define S3C_SYSREG(x) (S3C_VA_SYS + (x))
+
+#define S3C64XX_OTHERS S3C_SYSREG(0x900)
+
+#define S3C64XX_OTHERS_USBMASK (1 << 16)
+
+#endif /* _PLAT_REGS_SYS_H */
if (offs > 27)
return -EINVAL;
- if (offs > 15)
+ if (offs <= 15)
reg = S3C64XX_EINT0CON0;
else
reg = S3C64XX_EINT0CON1;
&clk_iis_cd1,
&clk_pcm_cd,
&clk_mout_epll.clk,
+ &clk_fout_epll,
&clk_mout_mpll.clk,
&clk_dout_mpll,
&clk_mmc0.clk,
projects / firefly-linux-kernel-4.4.55.git / commitdiff