if (MI->isCopy() && isFPCopy(MI))
FPInstClass = X86II::SpecialFP;
+ if (MI->isImplicitDef() &&
+ X86::RFP80RegClass.contains(MI->getOperand(0).getReg()))
+ FPInstClass = X86II::SpecialFP;
+
if (FPInstClass == X86II::NotFP)
continue; // Efficiently ignore non-fp insts!
break;
}
+ case TargetOpcode::IMPLICIT_DEF: {
+ // All FP registers must be explicitly defined, so load a 0 instead.
+ unsigned Reg = MI->getOperand(0).getReg() - X86::FP0;
+ DEBUG(dbgs() << "Emitting LD_F0 for implicit FP" << Reg << '\n');
+ BuildMI(*MBB, I, MI->getDebugLoc(), TII->get(X86::LD_F0));
+ pushReg(Reg);
+ break;
+ }
+
case X86::FpPOP_RETVAL: {
// The FpPOP_RETVAL instruction is used after calls that return a value on
// the floating point stack. We cannot model this with ST defs since CALL
-; RUN: llc %s -O0 -fast-isel -regalloc=fast -o -
+; RUN: llc %s -O0 -fast-isel -regalloc=fast -mcpu=i386 -o -
; PR4767
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
if.end: ; preds = %if.then, %cond.false, %cond.true
ret void
}
+
+; PR10575
+; This produces a FP0 = IMPLICIT_DEF instruction.
+define void @__m_rankmerge_MOD_dindexmerge_() nounwind {
+entry:
+ br label %"20"
+
+"20": ; preds = %"23", %entry
+ %0 = phi double [ undef, %entry ], [ %0, %"23" ]
+ %1 = phi double [ 0.000000e+00, %entry ], [ %2, %"23" ]
+ br i1 undef, label %"21", label %"23"
+
+"21": ; preds = %"20"
+ ret void
+
+"23": ; preds = %"20"
+ %2 = select i1 undef, double %0, double %1
+ br label %"20"
+}