If sink max TMDS clock < 340MHz, we think the mode pixel clock
greater than 340MHz should support YCbCr420, or it is a bad mode.
Change-Id: I9f53fa4f9875977ae0355b65d9ccd8a304558c5d
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
*/
if (mode->clock > INT_MAX / 1000)
return MODE_BAD;
+ /*
+ * If sink max TMDS clock < 340MHz, we should check the mode pixel
+ * clock > 340MHz is YCbCr420 or not.
+ */
+ if (mode->clock > 340000 &&
+ connector->display_info.max_tmds_clock < 340000 &&
+ !(mode->flags & DRM_MODE_FLAG_420_MASK))
+ return MODE_BAD;
if (!encoder) {
const struct drm_connector_helper_funcs *funcs;