ARM: Add Tauros2 L2 cache controller support
authorLennert Buytenhek <buytenh@marvell.com>
Tue, 24 Nov 2009 17:33:52 +0000 (19:33 +0200)
committerNicolas Pitre <nico@fluxnic.net>
Fri, 27 Nov 2009 20:43:21 +0000 (15:43 -0500)
Support for the Tauros2 L2 cache controller as used with the PJ1
and PJ4 CPUs.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
arch/arm/configs/dove_defconfig
arch/arm/include/asm/hardware/cache-tauros2.h [new file with mode: 0644]
arch/arm/mach-dove/common.c
arch/arm/mm/Kconfig
arch/arm/mm/Makefile
arch/arm/mm/cache-tauros2.c [new file with mode: 0644]

index f2d1ea0abb849a7402d03ba688adaacb6f03b5d8..837bb522d462bcc92aafdfa6aad7c2f54b37d00d 100644 (file)
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.32-rc6
-# Tue Nov 24 13:48:39 2009
+# Tue Nov 24 13:51:23 2009
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -207,6 +207,8 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_ICACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_CACHE_TAUROS2=y
 CONFIG_ARM_L1_CACHE_SHIFT=5
 # CONFIG_ARM_ERRATA_411920 is not set
 
diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h
new file mode 100644 (file)
index 0000000..538f17c
--- /dev/null
@@ -0,0 +1,11 @@
+/*
+ * arch/arm/include/asm/hardware/cache-tauros2.h
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+extern void __init tauros2_init(void);
index a20cf099cd97725708ea607af253a7cff7425e59..806972a68c87344c0628cbe72bfb74e1944bb1c6 100644 (file)
@@ -24,6 +24,7 @@
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <asm/timex.h>
+#include <asm/hardware/cache-tauros2.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/mach/pci.h>
@@ -760,6 +761,9 @@ void __init dove_init(void)
        printk(KERN_INFO "Dove 88AP510 SoC, ");
        printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000);
 
+#ifdef CONFIG_CACHE_TAUROS2
+       tauros2_init();
+#endif
        dove_setup_cpu_mbus();
 
        dove_ge00_shared_data.t_clk = tclk;
index 1549863d7b54564b131d2f415815d51b68c6057b..4958ef2c6254d0d8c7bbb1d07a4f41871d93d12f 100644 (file)
@@ -764,6 +764,15 @@ config CACHE_L2X0
        help
          This option enables the L2x0 PrimeCell.
 
+config CACHE_TAUROS2
+       bool "Enable the Tauros2 L2 cache controller"
+       depends on ARCH_DOVE
+       default y
+       select OUTER_CACHE
+       help
+         This option enables the Tauros2 L2 cache controller (as
+         found on PJ1/PJ4).
+
 config CACHE_XSC3L2
        bool "Enable the L2 cache on XScale3"
        depends on CPU_XSC3
index 055cb2aa8134c63fba47cdfbc6192e3ec3ffd2f6..06bcf2e738582e86485220764df3054c10edc5d8 100644 (file)
@@ -87,4 +87,4 @@ obj-$(CONFIG_CPU_V7)          += proc-v7.o
 obj-$(CONFIG_CACHE_FEROCEON_L2)        += cache-feroceon-l2.o
 obj-$(CONFIG_CACHE_L2X0)       += cache-l2x0.o
 obj-$(CONFIG_CACHE_XSC3L2)     += cache-xsc3l2.o
-
+obj-$(CONFIG_CACHE_TAUROS2)    += cache-tauros2.o
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
new file mode 100644 (file)
index 0000000..5086865
--- /dev/null
@@ -0,0 +1,263 @@
+/*
+ * arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * References:
+ * - PJ1 CPU Core Datasheet,
+ *   Document ID MV-S104837-01, Rev 0.7, January 24 2008.
+ * - PJ4 CPU Core Datasheet,
+ *   Document ID MV-S105190-00, Rev 0.7, March 14 2008.
+ */
+
+#include <linux/init.h>
+#include <asm/cacheflush.h>
+#include <asm/hardware/cache-tauros2.h>
+
+
+/*
+ * When Tauros2 is used on a CPU that supports the v7 hierarchical
+ * cache operations, the cache handling code in proc-v7.S takes care
+ * of everything, including handling DMA coherency.
+ *
+ * So, we only need to register outer cache operations here if we're
+ * being used on a pre-v7 CPU, and we only need to build support for
+ * outer cache operations into the kernel image if the kernel has been
+ * configured to support a pre-v7 CPU.
+ */
+#if __LINUX_ARM_ARCH__ < 7
+/*
+ * Low-level cache maintenance operations.
+ */
+static inline void tauros2_clean_pa(unsigned long addr)
+{
+       __asm__("mcr p15, 1, %0, c7, c11, 3" : : "r" (addr));
+}
+
+static inline void tauros2_clean_inv_pa(unsigned long addr)
+{
+       __asm__("mcr p15, 1, %0, c7, c15, 3" : : "r" (addr));
+}
+
+static inline void tauros2_inv_pa(unsigned long addr)
+{
+       __asm__("mcr p15, 1, %0, c7, c7, 3" : : "r" (addr));
+}
+
+
+/*
+ * Linux primitives.
+ *
+ * Note that the end addresses passed to Linux primitives are
+ * noninclusive.
+ */
+#define CACHE_LINE_SIZE                32
+
+static void tauros2_inv_range(unsigned long start, unsigned long end)
+{
+       /*
+        * Clean and invalidate partial first cache line.
+        */
+       if (start & (CACHE_LINE_SIZE - 1)) {
+               tauros2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
+               start = (start | (CACHE_LINE_SIZE - 1)) + 1;
+       }
+
+       /*
+        * Clean and invalidate partial last cache line.
+        */
+       if (end & (CACHE_LINE_SIZE - 1)) {
+               tauros2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
+               end &= ~(CACHE_LINE_SIZE - 1);
+       }
+
+       /*
+        * Invalidate all full cache lines between 'start' and 'end'.
+        */
+       while (start < end) {
+               tauros2_inv_pa(start);
+               start += CACHE_LINE_SIZE;
+       }
+
+       dsb();
+}
+
+static void tauros2_clean_range(unsigned long start, unsigned long end)
+{
+       start &= ~(CACHE_LINE_SIZE - 1);
+       while (start < end) {
+               tauros2_clean_pa(start);
+               start += CACHE_LINE_SIZE;
+       }
+
+       dsb();
+}
+
+static void tauros2_flush_range(unsigned long start, unsigned long end)
+{
+       start &= ~(CACHE_LINE_SIZE - 1);
+       while (start < end) {
+               tauros2_clean_inv_pa(start);
+               start += CACHE_LINE_SIZE;
+       }
+
+       dsb();
+}
+#endif
+
+static inline u32 __init read_extra_features(void)
+{
+       u32 u;
+
+       __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u));
+
+       return u;
+}
+
+static inline void __init write_extra_features(u32 u)
+{
+       __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
+}
+
+static void __init disable_l2_prefetch(void)
+{
+       u32 u;
+
+       /*
+        * Read the CPU Extra Features register and verify that the
+        * Disable L2 Prefetch bit is set.
+        */
+       u = read_extra_features();
+       if (!(u & 0x01000000)) {
+               printk(KERN_INFO "Tauros2: Disabling L2 prefetch.\n");
+               write_extra_features(u | 0x01000000);
+       }
+}
+
+static inline int __init cpuid_scheme(void)
+{
+       extern int processor_id;
+
+       return !!((processor_id & 0x000f0000) == 0x000f0000);
+}
+
+static inline u32 __init read_mmfr3(void)
+{
+       u32 mmfr3;
+
+       __asm__("mrc p15, 0, %0, c0, c1, 7\n" : "=r" (mmfr3));
+
+       return mmfr3;
+}
+
+static inline u32 __init read_actlr(void)
+{
+       u32 actlr;
+
+       __asm__("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));
+
+       return actlr;
+}
+
+static inline void __init write_actlr(u32 actlr)
+{
+       __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr));
+}
+
+void __init tauros2_init(void)
+{
+       extern int processor_id;
+       char *mode;
+
+       disable_l2_prefetch();
+
+#ifdef CONFIG_CPU_32v5
+       if ((processor_id & 0xff0f0000) == 0x56050000) {
+               u32 feat;
+
+               /*
+                * v5 CPUs with Tauros2 have the L2 cache enable bit
+                * located in the CPU Extra Features register.
+                */
+               feat = read_extra_features();
+               if (!(feat & 0x00400000)) {
+                       printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
+                       write_extra_features(feat | 0x00400000);
+               }
+
+               mode = "ARMv5";
+               outer_cache.inv_range = tauros2_inv_range;
+               outer_cache.clean_range = tauros2_clean_range;
+               outer_cache.flush_range = tauros2_flush_range;
+       }
+#endif
+
+#ifdef CONFIG_CPU_32v6
+       /*
+        * Check whether this CPU lacks support for the v7 hierarchical
+        * cache ops.  (PJ4 is in its v6 personality mode if the MMFR3
+        * register indicates no support for the v7 hierarchical cache
+        * ops.)
+        */
+       if (cpuid_scheme() && (read_mmfr3() & 0xf) == 0) {
+               /*
+                * When Tauros2 is used in an ARMv6 system, the L2
+                * enable bit is in the ARMv6 ARM-mandated position
+                * (bit [26] of the System Control Register).
+                */
+               if (!(get_cr() & 0x04000000)) {
+                       printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
+                       adjust_cr(0x04000000, 0x04000000);
+               }
+
+               mode = "ARMv6";
+               outer_cache.inv_range = tauros2_inv_range;
+               outer_cache.clean_range = tauros2_clean_range;
+               outer_cache.flush_range = tauros2_flush_range;
+       }
+#endif
+
+#ifdef CONFIG_CPU_32v7
+       /*
+        * Check whether this CPU has support for the v7 hierarchical
+        * cache ops.  (PJ4 is in its v7 personality mode if the MMFR3
+        * register indicates support for the v7 hierarchical cache
+        * ops.)
+        *
+        * (Although strictly speaking there may exist CPUs that
+        * implement the v7 cache ops but are only ARMv6 CPUs (due to
+        * not complying with all of the other ARMv7 requirements),
+        * there are no real-life examples of Tauros2 being used on
+        * such CPUs as of yet.)
+        */
+       if (cpuid_scheme() && (read_mmfr3() & 0xf) == 1) {
+               u32 actlr;
+
+               /*
+                * When Tauros2 is used in an ARMv7 system, the L2
+                * enable bit is located in the Auxiliary System Control
+                * Register (which is the only register allowed by the
+                * ARMv7 spec to contain fine-grained cache control bits).
+                */
+               actlr = read_actlr();
+               if (!(actlr & 0x00000002)) {
+                       printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
+                       write_actlr(actlr | 0x00000002);
+               }
+
+               mode = "ARMv7";
+       }
+#endif
+
+       if (mode == NULL) {
+               printk(KERN_CRIT "Tauros2: Unable to detect CPU mode.\n");
+               return;
+       }
+
+       printk(KERN_INFO "Tauros2: L2 cache support initialised "
+                        "in %s mode.\n", mode);
+}