Fix a typo in a comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89360 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.td b/lib/Target/Blackfin/BlackfinRegisterInfo.td
index 642d10f5aa67f84018a529dcfcc101fde821f4a0..d396cc807e88ee347f80575587d18a04507bb661 100644 (file)
--- a/lib/Target/Blackfin/BlackfinRegisterInfo.td
+++ b/lib/Target/Blackfin/BlackfinRegisterInfo.td
@@ -44,7 +44,7 @@ class Ra<bits<3> num, string n, list<Register> subs> : BlackfinReg<n> {
   let Num = num;
 }
 
-// Ywo halves of 32-bit register
+// Two halves of 32-bit register
 multiclass Rss<bits<3> group, bits<3> num, string n> {
   def H : Rs<group, num, 1, !strconcat(n, ".h")>;
   def L : Rs<group, num, 0, !strconcat(n, ".l")>;