; RUN: llc -march=mips < %s | FileCheck %s
-; CHECK: madd $5, $4
+; CHECK: madd
define i64 @madd1(i32 %a, i32 %b, i32 %c) nounwind readnone {
entry:
%conv = sext i32 %a to i64
ret i64 %add
}
-; CHECK: maddu $5, $4
+; CHECK: maddu
define i64 @madd2(i32 %a, i32 %b, i32 %c) nounwind readnone {
entry:
%conv = zext i32 %a to i64
ret i64 %add
}
-; CHECK: madd $5, $4
+; CHECK: madd
define i64 @madd3(i32 %a, i32 %b, i64 %c) nounwind readnone {
entry:
%conv = sext i32 %a to i64
ret i64 %add
}
-; CHECK: msub $5, $4
+; CHECK: msub
define i64 @msub1(i32 %a, i32 %b, i32 %c) nounwind readnone {
entry:
%conv = sext i32 %c to i64
ret i64 %sub
}
-; CHECK: msubu $5, $4
+; CHECK: msubu
define i64 @msub2(i32 %a, i32 %b, i32 %c) nounwind readnone {
entry:
%conv = zext i32 %c to i64
ret i64 %sub
}
-; CHECK: msub $5, $4
+; CHECK: msub
define i64 @msub3(i32 %a, i32 %b, i64 %c) nounwind readnone {
entry:
%conv = sext i32 %a to i64
; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
-; CHECK: rotrv $2, $4, $2
+; CHECK: rotrv $2, $4
define i32 @rot0(i32 %a, i32 %b) nounwind readnone {
entry:
%shl = shl i32 %a, %b