phy: rockchip-inno-usb2: add otg-port support for rk3328

This patch adds otg-port configuration for rk3328 SoC.

Change-Id: Ic680c7f345396c129e7b2ea8a8dded8ba6ee0ae9
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
index dc6fdd508fd15b674dec06ca000668d808b80ae3..a4468d9420c2441a455c4f702d40219fca32515e 100644 (file)
--- a/drivers/phy/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/phy-rockchip-inno-usb2.c
@@ -1528,6 +1528,25 @@ static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
                .phy_tuning     = rk3328_usb2phy_tuning,
                .clkout_ctl     = { 0x108, 4, 4, 1, 0 },
                .port_cfgs      = {
+                       [USB2PHY_PORT_OTG] = {
+                               .phy_sus        = { 0x0100, 15, 0, 0, 0x1d1 },
+                               .bvalid_det_en  = { 0x0110, 2, 2, 0, 1 },
+                               .bvalid_det_st  = { 0x0114, 2, 2, 0, 1 },
+                               .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
+                               .idfall_det_en  = { 0x0110, 5, 5, 0, 1 },
+                               .idfall_det_st  = { 0x0114, 5, 5, 0, 1 },
+                               .idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
+                               .idrise_det_en  = { 0x0110, 4, 4, 0, 1 },
+                               .idrise_det_st  = { 0x0114, 4, 4, 0, 1 },
+                               .idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
+                               .ls_det_en      = { 0x0110, 0, 0, 0, 1 },
+                               .ls_det_st      = { 0x0114, 0, 0, 0, 1 },
+                               .ls_det_clr     = { 0x0118, 0, 0, 0, 1 },
+                               .utmi_avalid    = { 0x0120, 10, 10, 0, 1 },
+                               .utmi_bvalid    = { 0x0120, 9, 9, 0, 1 },
+                               .utmi_iddig     = { 0x0120, 6, 6, 0, 1 },
+                               .utmi_ls        = { 0x0120, 5, 4, 0, 1 },
+                       },
                        [USB2PHY_PORT_HOST] = {
                                .phy_sus        = { 0x104, 15, 0, 0, 0x1d1 },
                                .ls_det_en      = { 0x110, 1, 1, 0, 1 },
@@ -1537,6 +1556,18 @@ static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
                                .utmi_hstdet    = { 0x120, 19, 19, 0, 1 }
                        }
                },
+               .chg_det = {
+                       .opmode         = { 0x0100, 3, 0, 5, 1 },
+                       .cp_det         = { 0x0120, 24, 24, 0, 1 },
+                       .dcp_det        = { 0x0120, 23, 23, 0, 1 },
+                       .dp_det         = { 0x0120, 25, 25, 0, 1 },
+                       .idm_sink_en    = { 0x0108, 8, 8, 0, 1 },
+                       .idp_sink_en    = { 0x0108, 7, 7, 0, 1 },
+                       .idp_src_en     = { 0x0108, 9, 9, 0, 1 },
+                       .rdm_pdwn_en    = { 0x0108, 10, 10, 0, 1 },
+                       .vdm_src_en     = { 0x0108, 12, 12, 0, 1 },
+                       .vdp_src_en     = { 0x0108, 11, 11, 0, 1 },
+               },
        },
        { /* sentinel */ }
 };