} else {
ArgVT = VT;
}
+
+ ISD::LoadExtType LoadType = ISD::EXTLOAD;
+ if (Ins[i].Flags.isZExt()) {
+ LoadType = ISD::ZEXTLOAD;
+ } else if (Ins[i].Flags.isSExt()) {
+ LoadType = ISD::SEXTLOAD;
+ }
+
PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
AMDGPUAS::PARAM_I_ADDRESS);
- SDValue Arg = DAG.getExtLoad(ISD::ZEXTLOAD, DL, VT, DAG.getRoot(),
+ SDValue Arg = DAG.getExtLoad(LoadType, DL, VT, DAG.getRoot(),
DAG.getConstant(ParamOffsetBytes, MVT::i32),
MachinePointerInfo(UndefValue::get(PtrTy)),
ArgVT, false, false, ArgBytes);
ret void
}
+; CHECK: @i8_sext_arg
+; CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
+define void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 signext %in) nounwind {
+entry:
+ %0 = sext i8 %in to i32
+ store i32 %0, i32 addrspace(1)* %out, align 4
+ ret void
+}
+
; CHECK: @i16_arg
; CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}
store i32 %0, i32 addrspace(1)* %out, align 4
ret void
}
+
+; CHECK: @i16_sext_arg
+; CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}
+
+define void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 signext %in) nounwind {
+entry:
+ %0 = sext i16 %in to i32
+ store i32 %0, i32 addrspace(1)* %out, align 4
+ ret void
+}