memory: tegra: Add Tegra210 support
authorThierry Reding <treding@nvidia.com>
Mon, 23 Mar 2015 09:45:12 +0000 (10:45 +0100)
committerThierry Reding <treding@nvidia.com>
Thu, 13 Aug 2015 14:07:52 +0000 (16:07 +0200)
Add the table of memory clients and SWGROUPs for Tegra210 to enable SMMU
support for this new SoC.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/iommu/Kconfig
drivers/memory/tegra/Makefile
drivers/memory/tegra/mc.c
drivers/memory/tegra/mc.h
drivers/memory/tegra/tegra210.c [new file with mode: 0644]
include/dt-bindings/memory/tegra210-mc.h [new file with mode: 0644]

index f1fb1d3ccc56e679dd72334b6f81195981fa17c1..f491aec95160df84290237020bd4f2447af320dd 100644 (file)
@@ -222,7 +222,7 @@ config TEGRA_IOMMU_SMMU
        select IOMMU_API
        help
          This driver supports the IOMMU hardware (SMMU) found on NVIDIA Tegra
-         SoCs (Tegra30 up to Tegra132).
+         SoCs (Tegra30 up to Tegra210).
 
 config EXYNOS_IOMMU
        bool "Exynos IOMMU Support"
index 6a0b9ac54f0517927456b014b5e940da9b07518c..c2cb671ffc4ac453c6decfa159f68547b8c255b8 100644 (file)
@@ -4,6 +4,7 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC)  += tegra30.o
 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
+tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
 
 obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
 
index 5d10c9285f34736956e45984bd3dedab097c1c9e..a1ae0cc2b86d50dd24e84cf66871dd3148d86e01 100644 (file)
@@ -65,6 +65,9 @@ static const struct of_device_id tegra_mc_of_match[] = {
 #endif
 #ifdef CONFIG_ARCH_TEGRA_132_SOC
        { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
+#endif
+#ifdef CONFIG_ARCH_TEGRA_210_SOC
+       { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
 #endif
        { }
 };
index b7361b0a66964ce9a95dc02114cd276d759b6b60..ddb16676c3af4d99b59e62b84d77d0bdb30b5158 100644 (file)
@@ -41,4 +41,8 @@ extern const struct tegra_mc_soc tegra124_mc_soc;
 extern const struct tegra_mc_soc tegra132_mc_soc;
 #endif
 
+#ifdef CONFIG_ARCH_TEGRA_210_SOC
+extern const struct tegra_mc_soc tegra210_mc_soc;
+#endif
+
 #endif /* MEMORY_TEGRA_MC_H */
diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
new file mode 100644 (file)
index 0000000..5e144ab
--- /dev/null
@@ -0,0 +1,1080 @@
+/*
+ * Copyright (C) 2015 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/of.h>
+#include <linux/mm.h>
+
+#include <asm/cacheflush.h>
+
+#include <dt-bindings/memory/tegra210-mc.h>
+
+#include "mc.h"
+
+static const struct tegra_mc_client tegra210_mc_clients[] = {
+       {
+               .id = 0x00,
+               .name = "ptcr",
+               .swgroup = TEGRA_SWGROUP_PTC,
+       }, {
+               .id = 0x01,
+               .name = "display0a",
+               .swgroup = TEGRA_SWGROUP_DC,
+               .smmu = {
+                       .reg = 0x228,
+                       .bit = 1,
+               },
+               .la = {
+                       .reg = 0x2e8,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0xc2,
+               },
+       }, {
+               .id = 0x02,
+               .name = "display0ab",
+               .swgroup = TEGRA_SWGROUP_DCB,
+               .smmu = {
+                       .reg = 0x228,
+                       .bit = 2,
+               },
+               .la = {
+                       .reg = 0x2f4,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0xc6,
+               },
+       }, {
+               .id = 0x03,
+               .name = "display0b",
+               .swgroup = TEGRA_SWGROUP_DC,
+               .smmu = {
+                       .reg = 0x228,
+                       .bit = 3,
+               },
+               .la = {
+                       .reg = 0x2e8,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x50,
+               },
+       }, {
+               .id = 0x04,
+               .name = "display0bb",
+               .swgroup = TEGRA_SWGROUP_DCB,
+               .smmu = {
+                       .reg = 0x228,
+                       .bit = 4,
+               },
+               .la = {
+                       .reg = 0x2f4,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x50,
+               },
+       }, {
+               .id = 0x05,
+               .name = "display0c",
+               .swgroup = TEGRA_SWGROUP_DC,
+               .smmu = {
+                       .reg = 0x228,
+                       .bit = 5,
+               },
+               .la = {
+                       .reg = 0x2ec,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x50,
+               },
+       }, {
+               .id = 0x06,
+               .name = "display0cb",
+               .swgroup = TEGRA_SWGROUP_DCB,
+               .smmu = {
+                       .reg = 0x228,
+                       .bit = 6,
+               },
+               .la = {
+                       .reg = 0x2f8,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x50,
+               },
+       }, {
+               .id = 0x0e,
+               .name = "afir",
+               .swgroup = TEGRA_SWGROUP_AFI,
+               .smmu = {
+                       .reg = 0x228,
+                       .bit = 14,
+               },
+               .la = {
+                       .reg = 0x2e0,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x13,
+               },
+       }, {
+               .id = 0x0f,
+               .name = "avpcarm7r",
+               .swgroup = TEGRA_SWGROUP_AVPC,
+               .smmu = {
+                       .reg = 0x228,
+                       .bit = 15,
+               },
+               .la = {
+                       .reg = 0x2e4,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x04,
+               },
+       }, {
+               .id = 0x10,
+               .name = "displayhc",
+               .swgroup = TEGRA_SWGROUP_DC,
+               .smmu = {
+                       .reg = 0x228,
+                       .bit = 16,
+               },
+               .la = {
+                       .reg = 0x2f0,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x50,
+               },
+       }, {
+               .id = 0x11,
+               .name = "displayhcb",
+               .swgroup = TEGRA_SWGROUP_DCB,
+               .smmu = {
+                       .reg = 0x228,
+                       .bit = 17,
+               },
+               .la = {
+                       .reg = 0x2fc,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x50,
+               },
+       }, {
+               .id = 0x15,
+               .name = "hdar",
+               .swgroup = TEGRA_SWGROUP_HDA,
+               .smmu = {
+                       .reg = 0x228,
+                       .bit = 21,
+               },
+               .la = {
+                       .reg = 0x318,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x24,
+               },
+       }, {
+               .id = 0x16,
+               .name = "host1xdmar",
+               .swgroup = TEGRA_SWGROUP_HC,
+               .smmu = {
+                       .reg = 0x228,
+                       .bit = 22,
+               },
+               .la = {
+                       .reg = 0x310,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x1e,
+               },
+       }, {
+               .id = 0x17,
+               .name = "host1xr",
+               .swgroup = TEGRA_SWGROUP_HC,
+               .smmu = {
+                       .reg = 0x228,
+                       .bit = 23,
+               },
+               .la = {
+                       .reg = 0x310,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x50,
+               },
+       }, {
+               .id = 0x1c,
+               .name = "nvencsrd",
+               .swgroup = TEGRA_SWGROUP_NVENC,
+               .smmu = {
+                       .reg = 0x228,
+                       .bit = 28,
+               },
+               .la = {
+                       .reg = 0x328,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x23,
+               },
+       }, {
+               .id = 0x1d,
+               .name = "ppcsahbdmar",
+               .swgroup = TEGRA_SWGROUP_PPCS,
+               .smmu = {
+                       .reg = 0x228,
+                       .bit = 29,
+               },
+               .la = {
+                       .reg = 0x344,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x49,
+               },
+       }, {
+               .id = 0x1e,
+               .name = "ppcsahbslvr",
+               .swgroup = TEGRA_SWGROUP_PPCS,
+               .smmu = {
+                       .reg = 0x228,
+                       .bit = 30,
+               },
+               .la = {
+                       .reg = 0x344,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x1a,
+               },
+       }, {
+               .id = 0x1f,
+               .name = "satar",
+               .swgroup = TEGRA_SWGROUP_SATA,
+               .smmu = {
+                       .reg = 0x228,
+                       .bit = 31,
+               },
+               .la = {
+                       .reg = 0x350,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x65,
+               },
+       }, {
+               .id = 0x27,
+               .name = "mpcorer",
+               .swgroup = TEGRA_SWGROUP_MPCORE,
+               .la = {
+                       .reg = 0x320,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x04,
+               },
+       }, {
+               .id = 0x2b,
+               .name = "nvencswr",
+               .swgroup = TEGRA_SWGROUP_NVENC,
+               .smmu = {
+                       .reg = 0x22c,
+                       .bit = 11,
+               },
+               .la = {
+                       .reg = 0x328,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x31,
+               .name = "afiw",
+               .swgroup = TEGRA_SWGROUP_AFI,
+               .smmu = {
+                       .reg = 0x22c,
+                       .bit = 17,
+               },
+               .la = {
+                       .reg = 0x2e0,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x32,
+               .name = "avpcarm7w",
+               .swgroup = TEGRA_SWGROUP_AVPC,
+               .smmu = {
+                       .reg = 0x22c,
+                       .bit = 18,
+               },
+               .la = {
+                       .reg = 0x2e4,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x35,
+               .name = "hdaw",
+               .swgroup = TEGRA_SWGROUP_HDA,
+               .smmu = {
+                       .reg = 0x22c,
+                       .bit = 21,
+               },
+               .la = {
+                       .reg = 0x318,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x36,
+               .name = "host1xw",
+               .swgroup = TEGRA_SWGROUP_HC,
+               .smmu = {
+                       .reg = 0x22c,
+                       .bit = 22,
+               },
+               .la = {
+                       .reg = 0x314,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x39,
+               .name = "mpcorew",
+               .swgroup = TEGRA_SWGROUP_MPCORE,
+               .la = {
+                       .reg = 0x320,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x3b,
+               .name = "ppcsahbdmaw",
+               .swgroup = TEGRA_SWGROUP_PPCS,
+               .smmu = {
+                       .reg = 0x22c,
+                       .bit = 27,
+               },
+               .la = {
+                       .reg = 0x348,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x3c,
+               .name = "ppcsahbslvw",
+               .swgroup = TEGRA_SWGROUP_PPCS,
+               .smmu = {
+                       .reg = 0x22c,
+                       .bit = 28,
+               },
+               .la = {
+                       .reg = 0x348,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x3d,
+               .name = "sataw",
+               .swgroup = TEGRA_SWGROUP_SATA,
+               .smmu = {
+                       .reg = 0x22c,
+                       .bit = 29,
+               },
+               .la = {
+                       .reg = 0x350,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x65,
+               },
+       }, {
+               .id = 0x44,
+               .name = "ispra",
+               .swgroup = TEGRA_SWGROUP_ISP2,
+               .smmu = {
+                       .reg = 0x230,
+                       .bit = 4,
+               },
+               .la = {
+                       .reg = 0x370,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x18,
+               },
+       }, {
+               .id = 0x46,
+               .name = "ispwa",
+               .swgroup = TEGRA_SWGROUP_ISP2,
+               .smmu = {
+                       .reg = 0x230,
+                       .bit = 6,
+               },
+               .la = {
+                       .reg = 0x374,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x47,
+               .name = "ispwb",
+               .swgroup = TEGRA_SWGROUP_ISP2,
+               .smmu = {
+                       .reg = 0x230,
+                       .bit = 7,
+               },
+               .la = {
+                       .reg = 0x374,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x4a,
+               .name = "xusb_hostr",
+               .swgroup = TEGRA_SWGROUP_XUSB_HOST,
+               .smmu = {
+                       .reg = 0x230,
+                       .bit = 10,
+               },
+               .la = {
+                       .reg = 0x37c,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x39,
+               },
+       }, {
+               .id = 0x4b,
+               .name = "xusb_hostw",
+               .swgroup = TEGRA_SWGROUP_XUSB_HOST,
+               .smmu = {
+                       .reg = 0x230,
+                       .bit = 11,
+               },
+               .la = {
+                       .reg = 0x37c,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x4c,
+               .name = "xusb_devr",
+               .swgroup = TEGRA_SWGROUP_XUSB_DEV,
+               .smmu = {
+                       .reg = 0x230,
+                       .bit = 12,
+               },
+               .la = {
+                       .reg = 0x380,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x39,
+               },
+       }, {
+               .id = 0x4d,
+               .name = "xusb_devw",
+               .swgroup = TEGRA_SWGROUP_XUSB_DEV,
+               .smmu = {
+                       .reg = 0x230,
+                       .bit = 13,
+               },
+               .la = {
+                       .reg = 0x380,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x4e,
+               .name = "isprab",
+               .swgroup = TEGRA_SWGROUP_ISP2B,
+               .smmu = {
+                       .reg = 0x230,
+                       .bit = 14,
+               },
+               .la = {
+                       .reg = 0x384,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x18,
+               },
+       }, {
+               .id = 0x50,
+               .name = "ispwab",
+               .swgroup = TEGRA_SWGROUP_ISP2B,
+               .smmu = {
+                       .reg = 0x230,
+                       .bit = 16,
+               },
+               .la = {
+                       .reg = 0x388,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x51,
+               .name = "ispwbb",
+               .swgroup = TEGRA_SWGROUP_ISP2B,
+               .smmu = {
+                       .reg = 0x230,
+                       .bit = 17,
+               },
+               .la = {
+                       .reg = 0x388,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x54,
+               .name = "tsecsrd",
+               .swgroup = TEGRA_SWGROUP_TSEC,
+               .smmu = {
+                       .reg = 0x230,
+                       .bit = 20,
+               },
+               .la = {
+                       .reg = 0x390,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x9b,
+               },
+       }, {
+               .id = 0x55,
+               .name = "tsecswr",
+               .swgroup = TEGRA_SWGROUP_TSEC,
+               .smmu = {
+                       .reg = 0x230,
+                       .bit = 21,
+               },
+               .la = {
+                       .reg = 0x390,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x56,
+               .name = "a9avpscr",
+               .swgroup = TEGRA_SWGROUP_A9AVP,
+               .smmu = {
+                       .reg = 0x230,
+                       .bit = 22,
+               },
+               .la = {
+                       .reg = 0x3a4,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x04,
+               },
+       }, {
+               .id = 0x57,
+               .name = "a9avpscw",
+               .swgroup = TEGRA_SWGROUP_A9AVP,
+               .smmu = {
+                       .reg = 0x230,
+                       .bit = 23,
+               },
+               .la = {
+                       .reg = 0x3a4,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x58,
+               .name = "gpusrd",
+               .swgroup = TEGRA_SWGROUP_GPU,
+               .smmu = {
+                       /* read-only */
+                       .reg = 0x230,
+                       .bit = 24,
+               },
+               .la = {
+                       .reg = 0x3c8,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x1a,
+               },
+       }, {
+               .id = 0x59,
+               .name = "gpuswr",
+               .swgroup = TEGRA_SWGROUP_GPU,
+               .smmu = {
+                       /* read-only */
+                       .reg = 0x230,
+                       .bit = 25,
+               },
+               .la = {
+                       .reg = 0x3c8,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x5a,
+               .name = "displayt",
+               .swgroup = TEGRA_SWGROUP_DC,
+               .smmu = {
+                       .reg = 0x230,
+                       .bit = 26,
+               },
+               .la = {
+                       .reg = 0x2f0,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x50,
+               },
+       }, {
+               .id = 0x60,
+               .name = "sdmmcra",
+               .swgroup = TEGRA_SWGROUP_SDMMC1A,
+               .smmu = {
+                       .reg = 0x234,
+                       .bit = 0,
+               },
+               .la = {
+                       .reg = 0x3b8,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x49,
+               },
+       }, {
+               .id = 0x61,
+               .name = "sdmmcraa",
+               .swgroup = TEGRA_SWGROUP_SDMMC2A,
+               .smmu = {
+                       .reg = 0x234,
+                       .bit = 1,
+               },
+               .la = {
+                       .reg = 0x3bc,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x49,
+               },
+       }, {
+               .id = 0x62,
+               .name = "sdmmcr",
+               .swgroup = TEGRA_SWGROUP_SDMMC3A,
+               .smmu = {
+                       .reg = 0x234,
+                       .bit = 2,
+               },
+               .la = {
+                       .reg = 0x3c0,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x49,
+               },
+       }, {
+               .id = 0x63,
+               .swgroup = TEGRA_SWGROUP_SDMMC4A,
+               .name = "sdmmcrab",
+               .smmu = {
+                       .reg = 0x234,
+                       .bit = 3,
+               },
+               .la = {
+                       .reg = 0x3c4,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x49,
+               },
+       }, {
+               .id = 0x64,
+               .name = "sdmmcwa",
+               .swgroup = TEGRA_SWGROUP_SDMMC1A,
+               .smmu = {
+                       .reg = 0x234,
+                       .bit = 4,
+               },
+               .la = {
+                       .reg = 0x3b8,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x65,
+               .name = "sdmmcwaa",
+               .swgroup = TEGRA_SWGROUP_SDMMC2A,
+               .smmu = {
+                       .reg = 0x234,
+                       .bit = 5,
+               },
+               .la = {
+                       .reg = 0x3bc,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x66,
+               .name = "sdmmcw",
+               .swgroup = TEGRA_SWGROUP_SDMMC3A,
+               .smmu = {
+                       .reg = 0x234,
+                       .bit = 6,
+               },
+               .la = {
+                       .reg = 0x3c0,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x67,
+               .name = "sdmmcwab",
+               .swgroup = TEGRA_SWGROUP_SDMMC4A,
+               .smmu = {
+                       .reg = 0x234,
+                       .bit = 7,
+               },
+               .la = {
+                       .reg = 0x3c4,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x6c,
+               .name = "vicsrd",
+               .swgroup = TEGRA_SWGROUP_VIC,
+               .smmu = {
+                       .reg = 0x234,
+                       .bit = 12,
+               },
+               .la = {
+                       .reg = 0x394,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x1a,
+               },
+       }, {
+               .id = 0x6d,
+               .name = "vicswr",
+               .swgroup = TEGRA_SWGROUP_VIC,
+               .smmu = {
+                       .reg = 0x234,
+                       .bit = 13,
+               },
+               .la = {
+                       .reg = 0x394,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x72,
+               .name = "viw",
+               .swgroup = TEGRA_SWGROUP_VI,
+               .smmu = {
+                       .reg = 0x234,
+                       .bit = 18,
+               },
+               .la = {
+                       .reg = 0x398,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x73,
+               .name = "displayd",
+               .swgroup = TEGRA_SWGROUP_DC,
+               .smmu = {
+                       .reg = 0x234,
+                       .bit = 19,
+               },
+               .la = {
+                       .reg = 0x3c8,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x50,
+               },
+       }, {
+               .id = 0x78,
+               .name = "nvdecsrd",
+               .swgroup = TEGRA_SWGROUP_NVDEC,
+               .smmu = {
+                       .reg = 0x234,
+                       .bit = 24,
+               },
+               .la = {
+                       .reg = 0x3d8,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x23,
+               },
+       }, {
+               .id = 0x79,
+               .name = "nvdecswr",
+               .swgroup = TEGRA_SWGROUP_NVDEC,
+               .smmu = {
+                       .reg = 0x234,
+                       .bit = 25,
+               },
+               .la = {
+                       .reg = 0x3d8,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x7a,
+               .name = "aper",
+               .swgroup = TEGRA_SWGROUP_APE,
+               .smmu = {
+                       .reg = 0x234,
+                       .bit = 26,
+               },
+               .la = {
+                       .reg = 0x3dc,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0xff,
+               },
+       }, {
+               .id = 0x7b,
+               .name = "apew",
+               .swgroup = TEGRA_SWGROUP_APE,
+               .smmu = {
+                       .reg = 0x234,
+                       .bit = 27,
+               },
+               .la = {
+                       .reg = 0x3dc,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x7e,
+               .name = "nvjpgsrd",
+               .swgroup = TEGRA_SWGROUP_NVJPG,
+               .smmu = {
+                       .reg = 0x234,
+                       .bit = 30,
+               },
+               .la = {
+                       .reg = 0x3e4,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x23,
+               },
+       }, {
+               .id = 0x7f,
+               .name = "nvjpgswr",
+               .swgroup = TEGRA_SWGROUP_NVJPG,
+               .smmu = {
+                       .reg = 0x234,
+                       .bit = 31,
+               },
+               .la = {
+                       .reg = 0x3e4,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x80,
+               .name = "sesrd",
+               .swgroup = TEGRA_SWGROUP_SE,
+               .smmu = {
+                       .reg = 0xb98,
+                       .bit = 0,
+               },
+               .la = {
+                       .reg = 0x3e0,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x2e,
+               },
+       }, {
+               .id = 0x81,
+               .name = "seswr",
+               .swgroup = TEGRA_SWGROUP_SE,
+               .smmu = {
+                       .reg = 0xb98,
+                       .bit = 1,
+               },
+               .la = {
+                       .reg = 0xb98,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x82,
+               .name = "axiapr",
+               .swgroup = TEGRA_SWGROUP_AXIAP,
+               .smmu = {
+                       .reg = 0xb98,
+                       .bit = 2,
+               },
+               .la = {
+                       .reg = 0x3a0,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0xff,
+               },
+       }, {
+               .id = 0x83,
+               .name = "axiapw",
+               .swgroup = TEGRA_SWGROUP_AXIAP,
+               .smmu = {
+                       .reg = 0xb98,
+                       .bit = 3,
+               },
+               .la = {
+                       .reg = 0x3a0,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x84,
+               .name = "etrr",
+               .swgroup = TEGRA_SWGROUP_ETR,
+               .smmu = {
+                       .reg = 0xb98,
+                       .bit = 4,
+               },
+               .la = {
+                       .reg = 0x3ec,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0xff,
+               },
+       }, {
+               .id = 0x85,
+               .name = "etrw",
+               .swgroup = TEGRA_SWGROUP_ETR,
+               .smmu = {
+                       .reg = 0xb98,
+                       .bit = 5,
+               },
+               .la = {
+                       .reg = 0x3ec,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0xff,
+               },
+       }, {
+               .id = 0x86,
+               .name = "tsecsrdb",
+               .swgroup = TEGRA_SWGROUP_TSECB,
+               .smmu = {
+                       .reg = 0xb98,
+                       .bit = 6,
+               },
+               .la = {
+                       .reg = 0x3f0,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x9b,
+               },
+       }, {
+               .id = 0x87,
+               .name = "tsecswrb",
+               .swgroup = TEGRA_SWGROUP_TSECB,
+               .smmu = {
+                       .reg = 0xb98,
+                       .bit = 7,
+               },
+               .la = {
+                       .reg = 0x3f0,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       }, {
+               .id = 0x88,
+               .name = "gpusrd2",
+               .swgroup = TEGRA_SWGROUP_GPU,
+               .smmu = {
+                       /* read-only */
+                       .reg = 0xb98,
+                       .bit = 8,
+               },
+               .la = {
+                       .reg = 0x3e8,
+                       .shift = 0,
+                       .mask = 0xff,
+                       .def = 0x1a,
+               },
+       }, {
+               .id = 0x89,
+               .name = "gpuswr2",
+               .swgroup = TEGRA_SWGROUP_GPU,
+               .smmu = {
+                       /* read-only */
+                       .reg = 0xb98,
+                       .bit = 9,
+               },
+               .la = {
+                       .reg = 0x3e8,
+                       .shift = 16,
+                       .mask = 0xff,
+                       .def = 0x80,
+               },
+       },
+};
+
+static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
+       { .name = "dc",        .swgroup = TEGRA_SWGROUP_DC,        .reg = 0x240 },
+       { .name = "dcb",       .swgroup = TEGRA_SWGROUP_DCB,       .reg = 0x244 },
+       { .name = "afi",       .swgroup = TEGRA_SWGROUP_AFI,       .reg = 0x238 },
+       { .name = "avpc",      .swgroup = TEGRA_SWGROUP_AVPC,      .reg = 0x23c },
+       { .name = "hda",       .swgroup = TEGRA_SWGROUP_HDA,       .reg = 0x254 },
+       { .name = "hc",        .swgroup = TEGRA_SWGROUP_HC,        .reg = 0x250 },
+       { .name = "nvenc",     .swgroup = TEGRA_SWGROUP_NVENC,     .reg = 0x264 },
+       { .name = "ppcs",      .swgroup = TEGRA_SWGROUP_PPCS,      .reg = 0x270 },
+       { .name = "sata",      .swgroup = TEGRA_SWGROUP_SATA,      .reg = 0x274 },
+       { .name = "isp2",      .swgroup = TEGRA_SWGROUP_ISP2,      .reg = 0x258 },
+       { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
+       { .name = "xusb_dev",  .swgroup = TEGRA_SWGROUP_XUSB_DEV,  .reg = 0x28c },
+       { .name = "isp2b",     .swgroup = TEGRA_SWGROUP_ISP2B,     .reg = 0xaa4 },
+       { .name = "tsec",      .swgroup = TEGRA_SWGROUP_TSEC,      .reg = 0x294 },
+       { .name = "a9avp",     .swgroup = TEGRA_SWGROUP_A9AVP,     .reg = 0x290 },
+       { .name = "gpu",       .swgroup = TEGRA_SWGROUP_GPU,       .reg = 0xaac },
+       { .name = "sdmmc1a",   .swgroup = TEGRA_SWGROUP_SDMMC1A,   .reg = 0xa94 },
+       { .name = "sdmmc2a",   .swgroup = TEGRA_SWGROUP_SDMMC2A,   .reg = 0xa98 },
+       { .name = "sdmmc3a",   .swgroup = TEGRA_SWGROUP_SDMMC3A,   .reg = 0xa9c },
+       { .name = "sdmmc4a",   .swgroup = TEGRA_SWGROUP_SDMMC4A,   .reg = 0xaa0 },
+       { .name = "vic",       .swgroup = TEGRA_SWGROUP_VIC,       .reg = 0x284 },
+       { .name = "vi",        .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },
+       { .name = "nvdec",     .swgroup = TEGRA_SWGROUP_NVDEC,     .reg = 0xab4 },
+       { .name = "ape",       .swgroup = TEGRA_SWGROUP_APE,       .reg = 0xab8 },
+       { .name = "nvjpg",     .swgroup = TEGRA_SWGROUP_NVJPG,     .reg = 0xac0 },
+       { .name = "se",        .swgroup = TEGRA_SWGROUP_SE,        .reg = 0xabc },
+       { .name = "axiap",     .swgroup = TEGRA_SWGROUP_AXIAP,     .reg = 0xacc },
+       { .name = "etr",       .swgroup = TEGRA_SWGROUP_ETR,       .reg = 0xad0 },
+       { .name = "tsecb",     .swgroup = TEGRA_SWGROUP_TSECB,     .reg = 0xad4 },
+};
+
+static const struct tegra_smmu_soc tegra210_smmu_soc = {
+       .clients = tegra210_mc_clients,
+       .num_clients = ARRAY_SIZE(tegra210_mc_clients),
+       .swgroups = tegra210_swgroups,
+       .num_swgroups = ARRAY_SIZE(tegra210_swgroups),
+       .supports_round_robin_arbitration = true,
+       .supports_request_limit = true,
+       .num_tlb_lines = 32,
+       .num_asids = 128,
+};
+
+const struct tegra_mc_soc tegra210_mc_soc = {
+       .clients = tegra210_mc_clients,
+       .num_clients = ARRAY_SIZE(tegra210_mc_clients),
+       .num_address_bits = 34,
+       .atom_size = 64,
+       .client_id_mask = 0xff,
+       .smmu = &tegra210_smmu_soc,
+};
diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h
new file mode 100644 (file)
index 0000000..d1731bc
--- /dev/null
@@ -0,0 +1,36 @@
+#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA210_MC_H
+
+#define TEGRA_SWGROUP_PTC      0
+#define TEGRA_SWGROUP_DC       1
+#define TEGRA_SWGROUP_DCB      2
+#define TEGRA_SWGROUP_AFI      3
+#define TEGRA_SWGROUP_AVPC     4
+#define TEGRA_SWGROUP_HDA      5
+#define TEGRA_SWGROUP_HC       6
+#define TEGRA_SWGROUP_NVENC    7
+#define TEGRA_SWGROUP_PPCS     8
+#define TEGRA_SWGROUP_SATA     9
+#define TEGRA_SWGROUP_MPCORE   10
+#define TEGRA_SWGROUP_ISP2     11
+#define TEGRA_SWGROUP_XUSB_HOST        12
+#define TEGRA_SWGROUP_XUSB_DEV 13
+#define TEGRA_SWGROUP_ISP2B    14
+#define TEGRA_SWGROUP_TSEC     15
+#define TEGRA_SWGROUP_A9AVP    16
+#define TEGRA_SWGROUP_GPU      17
+#define TEGRA_SWGROUP_SDMMC1A  18
+#define TEGRA_SWGROUP_SDMMC2A  19
+#define TEGRA_SWGROUP_SDMMC3A  20
+#define TEGRA_SWGROUP_SDMMC4A  21
+#define TEGRA_SWGROUP_VIC      22
+#define TEGRA_SWGROUP_VI       23
+#define TEGRA_SWGROUP_NVDEC    24
+#define TEGRA_SWGROUP_APE      25
+#define TEGRA_SWGROUP_NVJPG    26
+#define TEGRA_SWGROUP_SE       27
+#define TEGRA_SWGROUP_AXIAP    28
+#define TEGRA_SWGROUP_ETR      29
+#define TEGRA_SWGROUP_TSECB    30
+
+#endif