return ret;
}
+static int rk3328_usb2phy_tuning(struct rockchip_usb2phy *rphy)
+{
+ int ret;
+
+ /* Open debug mode for tuning */
+ ret = regmap_write(rphy->grf, 0x2c, 0xffff0400);
+ if (ret)
+ return ret;
+
+ /*
+ * Open HS pre-emphasize function to increase
+ * HS slew rate for host port
+ */
+ ret = regmap_write(rphy->grf, 0x30, 0xffff851d);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static int rk3366_usb2phy_tuning(struct rockchip_usb2phy *rphy)
{
unsigned int open_pre_emphasize = 0xffff851f;
#define ROCKCHIP_USB2PHY_DEV_PM NULL
#endif /* CONFIG_PM_SLEEP */
+static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
+ {
+ .reg = 0x100,
+ .num_ports = 2,
+ .phy_tuning = rk3328_usb2phy_tuning,
+ .clkout_ctl = { 0x108, 4, 4, 1, 0 },
+ .port_cfgs = {
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus = { 0x104, 15, 0, 0, 0x1d1 },
+ .ls_det_en = { 0x110, 1, 1, 0, 1 },
+ .ls_det_st = { 0x114, 1, 1, 0, 1 },
+ .ls_det_clr = { 0x118, 1, 1, 0, 1 },
+ .utmi_ls = { 0x120, 17, 16, 0, 1 },
+ .utmi_hstdet = { 0x120, 19, 19, 0, 1 }
+ }
+ },
+ },
+ { /* sentinel */ }
+};
+
static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
{
.reg = 0x700,
};
static const struct of_device_id rockchip_usb2phy_dt_match[] = {
+ { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
{}