struct regulator *ldo_18,*ldo_28;
ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
-
+ if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
+ printk("get cif ldo failed!\n");
+ return;
+ }
if(on == 0){
regulator_disable(ldo_28);
regulator_put(ldo_28);
else{
regulator_set_voltage(ldo_28, 2800000, 2800000);
regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
+ // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
regulator_put(ldo_28);
regulator_set_voltage(ldo_18, 1800000, 1800000);
// regulator_set_suspend_voltage(ldo, 1800000);
regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo));
+ // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
regulator_put(ldo_18);
}
}
{
mdelay(100);
if(IS_CIF0()){
- pmu_set_idle_request(IDLE_REQ_VIO, true);
+ // pmu_set_idle_request(IDLE_REQ_VIO, true);
cru_set_soft_reset(SOFT_RST_CIF0, true);
udelay(5);
cru_set_soft_reset(SOFT_RST_CIF0, false);
- pmu_set_idle_request(IDLE_REQ_VIO, false);
+ // pmu_set_idle_request(IDLE_REQ_VIO, false);
}else{
- pmu_set_idle_request(IDLE_REQ_VIO, true);
+ // pmu_set_idle_request(IDLE_REQ_VIO, true);
cru_set_soft_reset(SOFT_RST_CIF1, true);
udelay(5);
cru_set_soft_reset(SOFT_RST_CIF1, false);
- pmu_set_idle_request(IDLE_REQ_VIO, false);
+ // pmu_set_idle_request(IDLE_REQ_VIO, false);
}
}
write_cif_reg(pcdev->base,CIF_CIF_CTRL,AXI_BURST_16|MODE_ONEFRAME|DISABLE_CAPTURE); /* ddl@rock-chips.com : vip ahb burst 16 */