supports-emmc;
bootpart-no-access;
fifo-depth = <0x80>;
-
-
- mmc,caps = <(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED)>;
- mmc,ocr = <(MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)>;
- mmc,use_dma = <MMC_USE_DMA 2>;
- mmc,dma_ch = <EMMC_DMA_CHN>;
- mmc,int = <CONTROLLER_INT_DETECT>;
- mmc,emmc_is_selected = <1>;
+ bus-width = <4>;
+
+ //mmc,caps = <(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED)>;
+ // mmc,ocr = <(MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
+ // MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
+ // MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)>;
+ // mmc,use_dma = <MMC_USE_DMA 2>;
+ // mmc,dma_ch = <EMMC_DMA_CHN>;
+ // mmc,int = <CONTROLLER_INT_DETECT>;
+ // mmc,emmc_is_selected = <1>;
status = "okay";
};
card-detect-delay = <200>;
pwr-gpios = <&gpio3 GPIO_A1 GPIO_ACTIVE_LOW>; /*pwr_en = GPIO3_A1*/
fifo-depth = <0x100>;
+ bus-width = <4>;
+
- mmc,caps = <(MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED)>;
- mmc,ocr = <(MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)>;
- mmc,use_dma = <MMC_USE_DMA 0>;
- mmc,dma_ch = <SDMMC_DMA_CHN>;
- mmc,int = <CONTROLLER_INT_DETECT>;
- //mmc,int = <GPIO_INT_DETECT>;
- mmc,emmc_is_selected = <0>;
status = "okay";
};
supports-highspeed;
supports-sdio;
fifo-depth = <0x100>;
+ bus-width = <4>;
mmc,caps = <(MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED)>;
mmc,ocr = <(MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
////mmc,int = <GPIO_INT_DETECT>;
////OOB pin?
//mmc,emmc_is_selected = <0>;
- status = "okay";
+ status = "disabled";
};
/* Variations in Rockchip specific dw-mshc controller */
enum dw_mci_rockchip_type {
+ DW_MCI_TYPE_RK3188,
DW_MCI_TYPE_RK3288,
};
enum dw_mci_rockchip_type ctrl_type;
} rockchip_compat[] = {
{
+ .compatible = "rockchip,rk3188-sdmmc",
+ .ctrl_type = DW_MCI_TYPE_RK3188,
+ },{
.compatible = "rockchip,rk3288-sdmmc",
.ctrl_type = DW_MCI_TYPE_RK3288,
},
/* Common capabilities of RK32XX SoC */
static unsigned long rockchip_dwmmc_caps[4] = {
/*MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR | //Temporarily comment out!!!!!!, deleted by xbw, at 2014-03-12*/
- MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
+ MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23|MMC_CAP_UHS_SDR12|MMC_CAP_UHS_SDR25|MMC_CAP_UHS_SDR50,
MMC_CAP_CMD23,
MMC_CAP_CMD23,
MMC_CAP_CMD23,
};
+unsigned int rockchip_dwmmc_hold_reg[4] = {1,0,0,0};
+
static const struct dw_mci_drv_data rockchip_drv_data = {
.caps = rockchip_dwmmc_caps,
+ .hold_reg_flag = rockchip_dwmmc_hold_reg,
.init = dw_mci_rockchip_priv_init,
.setup_clock = dw_mci_rockchip_setup_clock,
.prepare_command = dw_mci_rockchip_prepare_command,
MMC_DBG_INFO_FUNC(host->mmc,"%d..%s start cmd=%d, arg=0x%x[%s]",__LINE__, __FUNCTION__,cmd->opcode, cmd->arg,mmc_hostname(host->mmc));
//dw_mci_regs_printk(host);
- mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START|SDMMC_CMD_USE_HOLD_REG); //always use SDMMC_CMD_USE_HOLD_REG
+ if(host->mmc->hold_reg_flag)
+ cmd_flags |= SDMMC_CMD_USE_HOLD_REG;//fix the value to 1 in some Soc,for example RK3188.
+
+ mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
}
static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
/* find out bus-width for a given slot */
static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
{
- struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
+ struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
u32 bus_wd = 1;
if (!np)
}
if (drv_data && drv_data->caps)
mmc->caps |= drv_data->caps[ctrl_id];
+ if (drv_data && drv_data->hold_reg_flag)
+ mmc->hold_reg_flag |= drv_data->hold_reg_flag[ctrl_id];
if (host->pdata->caps2)
mmc->caps2 = host->pdata->caps2;
/**
* dw_mci driver data - dw-mshc implementation specific driver data.
* @caps: mmc subsystem specified capabilities of the controller(s).
+ * @hold_reg_flag: Fixed the value of HOLG_REG
* @init: early implementation specific initialization.
* @setup_clock: implementation specific clock configuration.
* @prepare_command: handle CMD register extensions.
*/
struct dw_mci_drv_data {
unsigned long *caps;
+ unsigned int *hold_reg_flag;
int (*init)(struct dw_mci *host);
int (*setup_clock)(struct dw_mci *host);
void (*prepare_command)(struct dw_mci *host, u32 *cmdr);
#define MMC_DBG_ERR_FUNC(mmc_host,fmt, arg...) \\r
do{ \\r
if(mmc_debug_level >= MMC_DBG_ERROR) { \\r
- if(NULL != strpbrk(dbg_flag,mmc_hostname(mmc_host))) { \\r
+ if(strstr(dbg_flag,mmc_hostname(mmc_host))) { \\r
printk(DRIVER_PREFIX "ERROR " fmt "\n", ##arg);\\r
} \\r
} \\r
#define MMC_DBG_WARN_FUNC(mmc_host,fmt, arg...) \\r
do { \\r
if(mmc_debug_level >= MMC_DBG_WARN) { \\r
- if(NULL != strpbrk(dbg_flag,mmc_hostname(mmc_host))) { \\r
+ if(strstr(dbg_flag,mmc_hostname(mmc_host))) { \\r
printk(DRIVER_PREFIX "WARN " fmt "\n", ##arg);\\r
} \\r
} \\r
#define MMC_DBG_INFO_FUNC(mmc_host,fmt, arg...) \\r
do { \\r
if(mmc_debug_level >= MMC_DBG_INFO) { \\r
- if(NULL != strpbrk(dbg_flag,mmc_hostname(mmc_host))) { \\r
+ if(strstr(dbg_flag,mmc_hostname(mmc_host))) { \\r
printk(DRIVER_PREFIX "INFO " fmt "\n", ##arg);\\r
} \\r
} \\r
#define MMC_DBG_CMD_FUNC(mmc_host,fmt, arg...) \\r
do { \\r
if(mmc_debug_level >= MMC_DBG_CMD) { \\r
- if(NULL != strpbrk(dbg_flag,mmc_hostname(mmc_host))) { \\r
+ if(strstr(dbg_flag,mmc_hostname(mmc_host))) { \\r
printk(DRIVER_PREFIX "CMD " fmt "\n", ##arg);\\r
} \\r
} \\r
#define MMC_DBG_BOOT_FUNC(mmc_host,fmt, arg...) {printk(DRIVER_PREFIX "BOOT " fmt "\n", ##arg);}\r
#define MMC_DBG_ERR_FUNC(mmc_host,fmt, arg...)\r
#define MMC_DBG_WARN_FUNC(mmc_host,fmt, arg...)\r
-#define MMC_DBG_INFO_FUNC\r
+#define MMC_DBG_INFO_FUNC(mmc_host,fmt, arg...)\r
#define MMC_DBG_CMD_FUNC(mmc_host,fmt, arg...)\r
#endif\r
\r
#define RESTRICT_CARD_TYPE_SD (1 << 0) /*noted by XBW, Rockchip Co.Ld*/
#define RESTRICT_CARD_TYPE_SDIO (1 << 1)
#define RESTRICT_CARD_TYPE_EMMC (1 << 2)
+ unsigned int hold_reg_flag;//to fix the hold_reg value
+
#ifdef CONFIG_MMC_CLKGATE
int clk_requests; /* internal reference counter */
struct dw_mci_slot *slot[MAX_MCI_SLOTS];
struct mmc_host *mmc;
struct mmc_command *pre_cmd;
+ unsigned int hold_reg_flag;//to fix the hold_reg value
/* FIFO push and pull */
int fifo_depth;