Don't indent cases in a switch, no functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127681 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/lib/Target/XCore/XCoreISelDAGToDAG.cpp
index fc8a07aad73bb4ad3b74339d4992020398dbd76d..4d2ff81ad45606798ecd8bd466e571717745146f 100644 (file)
--- a/lib/Target/XCore/XCoreISelDAGToDAG.cpp
+++ b/lib/Target/XCore/XCoreISelDAGToDAG.cpp
@@ -157,58 +157,58 @@ SDNode *XCoreDAGToDAGISel::Select(SDNode *N) {
   EVT NVT = N->getValueType(0);
   if (NVT == MVT::i32) {
     switch (N->getOpcode()) {
-      default: break;
-      case ISD::Constant: {
-        uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue();
-        if (immMskBitp(N)) {
-          // Transformation function: get the size of a mask
-          // Look for the first non-zero bit
-          SDValue MskSize = getI32Imm(32 - CountLeadingZeros_32(Val));
-          return CurDAG->getMachineNode(XCore::MKMSK_rus, dl,
-                                        MVT::i32, MskSize);
-        }
-        else if (!isUInt<16>(Val)) {
-          SDValue CPIdx =
-            CurDAG->getTargetConstantPool(ConstantInt::get(
-                                  Type::getInt32Ty(*CurDAG->getContext()), Val),
-                                          TLI.getPointerTy());
-          return CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32, 
-                                        MVT::Other, CPIdx, 
-                                        CurDAG->getEntryNode());
-        }
-        break;
+    default: break;
+    case ISD::Constant: {
+      uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue();
+      if (immMskBitp(N)) {
+        // Transformation function: get the size of a mask
+        // Look for the first non-zero bit
+        SDValue MskSize = getI32Imm(32 - CountLeadingZeros_32(Val));
+        return CurDAG->getMachineNode(XCore::MKMSK_rus, dl,
+                                      MVT::i32, MskSize);
       }
-      case XCoreISD::LADD: {
-        SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
-                            N->getOperand(2) };
-        return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32,
-                                      Ops, 3);
+      else if (!isUInt<16>(Val)) {
+        SDValue CPIdx =
+          CurDAG->getTargetConstantPool(ConstantInt::get(
+                                Type::getInt32Ty(*CurDAG->getContext()), Val),
+                                        TLI.getPointerTy());
+        return CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32, 
+                                      MVT::Other, CPIdx, 
+                                      CurDAG->getEntryNode());
       }
-      case XCoreISD::LSUB: {
-        SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
-                            N->getOperand(2) };
-        return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32,
-                                      Ops, 3);
-      }
-      case XCoreISD::MACCU: {
-        SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
-                          N->getOperand(2), N->getOperand(3) };
-        return CurDAG->getMachineNode(XCore::MACCU_l4r, dl, MVT::i32, MVT::i32,
-                                      Ops, 4);
-      }
-      case XCoreISD::MACCS: {
-        SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
-                          N->getOperand(2), N->getOperand(3) };
-        return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32,
-                                      Ops, 4);
-      }
-      case XCoreISD::LMUL: {
-        SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
-                          N->getOperand(2), N->getOperand(3) };
-        return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32,
-                                      Ops, 4);
-      }
-      // Other cases are autogenerated.
+      break;
+    }
+    case XCoreISD::LADD: {
+      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
+                          N->getOperand(2) };
+      return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32,
+                                    Ops, 3);
+    }
+    case XCoreISD::LSUB: {
+      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
+                          N->getOperand(2) };
+      return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32,
+                                    Ops, 3);
+    }
+    case XCoreISD::MACCU: {
+      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
+                        N->getOperand(2), N->getOperand(3) };
+      return CurDAG->getMachineNode(XCore::MACCU_l4r, dl, MVT::i32, MVT::i32,
+                                    Ops, 4);
+    }
+    case XCoreISD::MACCS: {
+      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
+                        N->getOperand(2), N->getOperand(3) };
+      return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32,
+                                    Ops, 4);
+    }
+    case XCoreISD::LMUL: {
+      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
+                        N->getOperand(2), N->getOperand(3) };
+      return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32,
+                                    Ops, 4);
+    }
+    // Other cases are autogenerated.
     }
   }
   return SelectCode(N);