Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85965 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index c9b939de03deee18c8b892452755b50f1673c940..7c5b0f0bd83daa25a6da5b026e64d0cc5fcdde85 100644 (file)
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -448,7 +448,7 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
     case ARM::Int_eh_sjlj_setjmp:
       return 24;
     case ARM::t2Int_eh_sjlj_setjmp:
-      return 20;
+      return 22;
     case ARM::BR_JTr:
     case ARM::BR_JTm:
     case ARM::BR_JTadd:

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 26b57599d367d8394b543a6db785a4e320f976e1..5bfda370b93374f5ad4b543cabbad30b776f89de 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -1082,7 +1082,7 @@ let Defs =
                                AddrModeNone, SizeSpecial, NoItinerary,
                                "str.w\tsp, [$src, #+8] @ eh_setjmp begin\n"
                                "\tadr\tr12, 0f\n"
-                               "\torr\tr12, #1\n"
+                               "\torr.w\tr12, r12, #1\n"
                                "\tstr.w\tr12, [$src, #+4]\n"
                                "\tmovs\tr0, #0\n"
                                "\tb\t1f\n"