clk: rockchip: add clkops_rate_3288_usb480m

diff --git a/arch/arm/boot/dts/rk3288-clocks.dtsi b/arch/arm/boot/dts/rk3288-clocks.dtsi
index 379433bc7e06496bb0971a25213ba7e620ea7c32..2007b00926374396c6162e8695172e91d52330a6 100755 (executable)
--- a/arch/arm/boot/dts/rk3288-clocks.dtsi
+++ b/arch/arm/boot/dts/rk3288-clocks.dtsi
@@ -59,13 +59,6 @@
                                #clock-cells = <0>;
                        };
 
-                       dummy_480m: dummy_480m {
-                               compatible = "rockchip,rk-fixed-clock";
-                               clock-output-names = "dummy_480m";
-                               clock-frequency = <0>;
-                               #clock-cells = <0>;
-                       };
-
                        i2s_clkin: i2s_clkin {
                                compatible = "rockchip,rk-fixed-clock";
                                clock-output-names = "i2s_clkin";
@@ -955,12 +948,15 @@
                                                clocks = <&otgphy0_480m>, <&otgphy1_480m>, <&otgphy2_480m>;
                                                clock-output-names = "usbphy_480m";
                                                #clock-cells = <0>;
+                                               rockchip,clkops-idx =
+                                                       <CLKOPS_RATE_RK3288_USB480M>;
+                                               #clock-init-cells = <1>;
                                        };
 
                                        clk_uart0_pll: clk_uart0_pll_mux {
                                                compatible = "rockchip,rk3188-mux-con";
                                                rockchip,bits = <13 2>;
-                                               clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>, <&clk_npll>;
+                                               clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
                                                clock-output-names = "clk_uart0_pll";
                                                #clock-cells = <0>;
                                        };
@@ -1554,7 +1550,7 @@
                                        aclk_rga: aclk_rga_mux {
                                                compatible = "rockchip,rk3188-mux-con";
                                                rockchip,bits = <6 2>;
-                                               clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
+                                               clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
                                                clock-output-names = "aclk_rga";
                                                #clock-cells = <0>;
                                                #clock-init-cells = <1>;
@@ -1576,7 +1572,7 @@
                                        clk_rga: clk_rga_mux {
                                                compatible = "rockchip,rk3188-mux-con";
                                                rockchip,bits = <14 2>;
-                                               clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
+                                               clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
                                                clock-output-names = "clk_rga";
                                                #clock-cells = <0>;
                                                #clock-init-cells = <1>;
@@ -1605,7 +1601,7 @@
                                        aclk_vio0: aclk_vio0_mux {
                                                compatible = "rockchip,rk3188-mux-con";
                                                rockchip,bits = <6 2>;
-                                               clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
+                                               clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
                                                clock-output-names = "aclk_vio0";
                                                #clock-cells = <0>;
                                                #clock-init-cells = <1>;
@@ -1627,7 +1623,7 @@
                                        aclk_vio1: aclk_vio1_mux {
                                                compatible = "rockchip,rk3188-mux-con";
                                                rockchip,bits = <14 2>;
-                                               clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
+                                               clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
                                                clock-output-names = "aclk_vio1";
                                                #clock-cells = <0>;
                                                #clock-init-cells = <1>;
@@ -1656,7 +1652,7 @@
                                        clk_vepu: clk_vepu_mux {
                                                compatible = "rockchip,rk3188-mux-con";
                                                rockchip,bits = <6 2>;
-                                               clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
+                                               clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
                                                clock-output-names = "clk_vepu";
                                                #clock-cells = <0>;
                                                #clock-init-cells = <1>;
@@ -1678,7 +1674,7 @@
                                        clk_vdpu: clk_vdpu_mux {
                                                compatible = "rockchip,rk3188-mux-con";
                                                rockchip,bits = <14 2>;
-                                               clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
+                                               clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
                                                clock-output-names = "clk_vdpu";
                                                #clock-cells = <0>;
                                                #clock-init-cells = <1>;
@@ -1738,7 +1734,7 @@
                                        clk_gpu: clk_gpu_mux {
                                                compatible = "rockchip,rk3188-mux-con";
                                                rockchip,bits = <6 2>;
-                                               clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>, <&clk_npll>;
+                                               clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
                                                clock-output-names = "clk_gpu";
                                                #clock-cells = <0>;
                                                #clock-init-cells = <1>;

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 06b2e70277ad412ad89cdb6ec53dc9176c9372ff..662a0f256dadb462dc467393d28881b9f007b684 100755 (executable)
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -471,7 +471,7 @@
                rockchip,clocks-init-parent =
                        <&clk_core &clk_apll>,  <&aclk_bus_src &clk_gpll>,
                        <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
-                       <&clk_i2s_pll &clk_cpll>;
+                       <&clk_i2s_pll &clk_cpll>, <&usbphy_480m &otgphy2_480m>;
                rockchip,clocks-init-rate =
                        <&clk_core 792000000>,  <&clk_gpll 594000000>,
                        <&clk_cpll 384000000>,  <&clk_npll 500000000>,
@@ -585,6 +585,9 @@
                                /*UART*/
                                <&clk_gates11 9>,/*pclk_uart2*/
 
+                               /*480M*/
+                               <&usbphy_480m>,
+
                                /*PD*/
                                <&pd_gpu>,
                                <&pd_video>,

diff --git a/drivers/clk/rockchip/clk-ops.c b/drivers/clk/rockchip/clk-ops.c
index 8a803bd6d5cc03c57c43ce4558b234f58263ec6d..f74ce889d960ccfd0888f1d6c3efb381ebe57940 100644 (file)
--- a/drivers/clk/rockchip/clk-ops.c
+++ b/drivers/clk/rockchip/clk-ops.c
@@ -513,6 +513,52 @@ const struct clk_ops clkops_rate_3288_i2s = {
        .set_rate       = clk_3288_i2s_set_rate,
 };
 
+static bool usb480m_state = false;
+
+static long clk_3288_usb480m_determine_rate(struct clk_hw *hw, unsigned long rate,
+               unsigned long *best_parent_rate,
+               struct clk **best_parent_p)
+{
+       if(rate == 0)
+               return 0;
+       else
+               return 480*MHZ;
+}
+
+static long clk_3288_usb480m_round_rate(struct clk_hw *hw, unsigned long rate,
+               unsigned long *prate)
+{
+       return clk_3288_usb480m_determine_rate(hw, rate, prate, NULL);
+}
+
+static int clk_3288_usb480m_set_rate(struct clk_hw *hw, unsigned long rate,
+               unsigned long parent_rate)
+{
+       if(rate == 0)
+               usb480m_state = false;
+       else
+               usb480m_state = true;
+
+       return 0;
+}
+
+static unsigned long clk_3288_usb480m_recalc_rate(struct clk_hw *hw,
+               unsigned long parent_rate)
+{
+       if(usb480m_state)
+               return 480*MHZ;
+       else
+               return 0;
+}
+
+const struct clk_ops clkops_rate_3288_usb480m = {
+       .determine_rate = clk_3288_usb480m_determine_rate,
+       .set_rate       = clk_3288_usb480m_set_rate,
+       .round_rate     = clk_3288_usb480m_round_rate,
+       .recalc_rate    = clk_3288_usb480m_recalc_rate,
+};
+
+
 struct clk_ops_table rk_clkops_rate_table[] = {
        {.index = CLKOPS_RATE_MUX_DIV,          .clk_ops = &clkops_rate_auto_parent},
        {.index = CLKOPS_RATE_EVENDIV,          .clk_ops = &clkops_rate_evendiv},
@@ -523,6 +569,7 @@ struct clk_ops_table rk_clkops_rate_table[] = {
        {.index = CLKOPS_RATE_CORE_CHILD,       .clk_ops = &clkops_rate_core_peri},
        {.index = CLKOPS_RATE_DDR,              .clk_ops = &clkops_rate_ddr},
        {.index = CLKOPS_RATE_RK3288_I2S,       .clk_ops = &clkops_rate_3288_i2s},
+       {.index = CLKOPS_RATE_RK3288_USB480M,   .clk_ops = &clkops_rate_3288_usb480m},
        {.index = CLKOPS_RATE_I2S,              .clk_ops = NULL},
        {.index = CLKOPS_RATE_CIFOUT,           .clk_ops = NULL},
        {.index = CLKOPS_RATE_UART,             .clk_ops = NULL},

diff --git a/include/dt-bindings/clock/rockchip.h b/include/dt-bindings/clock/rockchip.h
index eb46c55dbad5e798a89fdfcd04a3043ed9f35d55..c482a54b2e938a7ce08cf6808d54fdfb4fdd00b6 100644 (file)
--- a/include/dt-bindings/clock/rockchip.h
+++ b/include/dt-bindings/clock/rockchip.h
@@ -51,6 +51,7 @@
 #define CLKOPS_RATE_CORE_CHILD         12
 #define CLKOPS_RATE_DDR                        13
 #define CLKOPS_RATE_RK3288_I2S         14
+#define CLKOPS_RATE_RK3288_USB480M     15
 #define CLKOPS_TABLE_END               (~0)
 
 /* pd id */