UPSTREAM: ARM: dts: rockchip: move rk3288 edp phy under the GRF

The edp-phy control is a part of the General Register Files and
with a recent patch in 4.6 the phy driver can now also handle this
correctly, so move the dts node under the GRF as well.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I6be6270739520f758dbe388cdbd50896c1d7d6f1
(cherry picked from commit 4b91545072ad7ca1963d2a89c8b42fc2eb561484)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 517e84071a8dd08ef4bdb49f608947b2fcd39594..56b3050c84756e69f3a6eef8d1b0aed58f6e1c4e 100644 (file)
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -204,15 +204,6 @@
                #clock-cells = <0>;
        };
 
-       edp_phy: edp-phy {
-               compatible = "rockchip,rk3288-dp-phy";
-               clocks = <&cru SCLK_EDP_24M>;
-               clock-names = "24m";
-               rockchip,grf = <&grf>;
-               #phy-cells = <0>;
-               status = "disabled";
-       };
-
        timer {
                compatible = "arm,armv7-timer";
                arm,cpu-registers-not-fw-configured;
@@ -855,6 +846,14 @@
        grf: syscon@ff770000 {
                compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
                reg = <0xff770000 0x1000>;
+
+               edp_phy: edp-phy {
+                       compatible = "rockchip,rk3288-dp-phy";
+                       clocks = <&cru SCLK_EDP_24M>;
+                       clock-names = "24m";
+                       #phy-cells = <0>;
+                       status = "disabled";
+               };
        };
 
        wdt: watchdog@ff800000 {