X86: allow registers 8-15 in test

This test was failing on some hosts when an unexpected register was used for a
variable. This just extends the regexp to allow the new x86-64 registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182929 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/zext-sext.ll b/test/CodeGen/X86/zext-sext.ll
index e4264aef4c16aeac7d9c7000bdb6f40418d1b976..2459f1fa254a405ed791cd725fb410c34361613f 100644 (file)
--- a/test/CodeGen/X86/zext-sext.ll
+++ b/test/CodeGen/X86/zext-sext.ll
@@ -33,9 +33,9 @@ entry:
   %tmp11 = sext i32 %tmp4 to i64
   %tmp12 = add i64 %tmp11, 5089792279245435153
 
-; CHECK:      addl     $2138875574, %e[[REGISTER_zext:[a-z]+]]
-; CHECK-NEXT: movslq   %e[[REGISTER_zext]], [[REGISTER_tmp:%[a-z]+]]
-; CHECK:      movq     [[REGISTER_tmp]], [[REGISTER_sext:%[a-z]+]]
+; CHECK:      addl     $2138875574, %e[[REGISTER_zext:[a-z0-9]+]]
+; CHECK-NEXT: movslq   %e[[REGISTER_zext]], [[REGISTER_tmp:%r[a-z0-9]+]]
+; CHECK:      movq     [[REGISTER_tmp]], [[REGISTER_sext:%r[a-z0-9]+]]
 ; CHECK-NEXT: subq     %r[[REGISTER_zext]], [[REGISTER_sext]]
 
   %tmp13 = sub i64 %tmp12, 2138875574