drm/i915: add Ironlake clock gating workaround for FDI link training
authorJesse Barnes <jbarnes@virtuousgeek.org>
Thu, 7 Oct 2010 23:01:15 +0000 (16:01 -0700)
committerChris Wilson <chris@chris-wilson.co.uk>
Fri, 8 Oct 2010 09:28:21 +0000 (10:28 +0100)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_display.c

index a72335e940f18afb2733028aa89ab4832806fc24..5a22887a5381b46915734ba54b41eac306bed637 100644 (file)
 #define FDI_RXA_CHICKEN         0xc200c
 #define FDI_RXB_CHICKEN         0xc2010
 #define  FDI_RX_PHASE_SYNC_POINTER_ENABLE       (1)
+#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, FDI_RXA_CHICKEN, FDI_RXB_CHICKEN)
 
 /* CPU: FDI_TX */
 #define FDI_TXA_CTL             0x60100
index 349710a8014c43ae52b32d4f6d6b51ae004c7f4f..5812fc7c5a0fd9646ce78ec1e24d27e091804025 100644 (file)
@@ -1714,6 +1714,9 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
        POSTING_READ(reg);
        udelay(150);
 
+       /* Ironlake workaround, enable clock pointer after FDI enable*/
+       I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
+
        reg = FDI_RX_IIR(pipe);
        for (tries = 0; tries < 5; tries++) {
                temp = I915_READ(reg);
@@ -2192,6 +2195,11 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
        POSTING_READ(reg);
        udelay(100);
 
+       /* Ironlake workaround, disable clock pointer after downing FDI */
+       I915_WRITE(FDI_RX_CHICKEN(pipe),
+                  I915_READ(FDI_RX_CHICKEN(pipe) &
+                            ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
+
        /* still set train pattern 1 */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);